drm/i915/psr: program vsc header for psr2

Function hsw_psr_setup handles vsc header setup for psr1 and
skl_psr_setup_vsc handles vsc header setup for psr2.

Setup VSC header in function skl_psr_setup_vsc for psr2 support,
as per edp 1.4 spec, table 6-11:VSC SDP HEADER Extension for psr2
operation.

v2: (Jani)
- Initialize variables to 0
- intel_dp_get_y_cord_status and intel_dp_get_y_cord_status made static
- Correct indentation for continuation lines
- Change DP_PSR_Y_COORDINATE to  DP_PSR2_SU_Y_COORDINATE_REQUIRED
- Change DPRX_FEATURE_ENUMERATION_LIST to DP_DPRX_*
- Change VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED to DP_VSC_*

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Jim Bride <jim.bride@linux.intel.com>
Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
Signed-off-by: Patil Deepti <deepti.patil@intel.com>
Reviewed-by: Jim Bride <jim.bride@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1483356663-32668-3-git-send-email-vathsala.nagaraju@intel.com

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 58c4408..2827dab 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1154,6 +1154,8 @@ struct i915_psr {
        bool psr2_support;
        bool aux_frame_sync;
        bool link_standby;
+       bool y_cord_support;
+       bool colorimetry_support;
 };
 
 enum intel_pch {

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 8c18f72..343e1d9 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3042,6 +3042,24 @@ intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_
                                DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
 }
 
+static bool intel_dp_get_y_cord_status(struct intel_dp *intel_dp)
+{
+       uint8_t psr_caps = 0;
+
+       drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_CAPS, &psr_caps);
+       return psr_caps & DP_PSR2_SU_Y_COORDINATE_REQUIRED;
+}
+
+static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
+{
+       uint8_t dprx = 0;
+
+       drm_dp_dpcd_readb(&intel_dp->aux,
+                       DP_DPRX_FEATURE_ENUMERATION_LIST,
+                       &dprx);
+       return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
+}
+
 /* These are source-specific values. */
 uint8_t
 intel_dp_voltage_max(struct intel_dp *intel_dp)
@@ -3620,6 +3638,14 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
                dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
                DRM_DEBUG_KMS("PSR2 %s on sink",
                              dev_priv->psr.psr2_support ? "supported" : "not supported");
+
+               if (dev_priv->psr.psr2_support) {
+                       dev_priv->psr.y_cord_support =
+                               intel_dp_get_y_cord_status(intel_dp);
+                       dev_priv->psr.colorimetry_support =
+                               intel_dp_get_colorimetry_status(intel_dp);
+               }
+
        }
 
        /* Read the eDP Display control capabilities registers */

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 6aca8ff..c3aa649 100644 (file)
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -122,13 +122,26 @@ static void vlv_psr_setup_vsc(struct intel_dp *intel_dp)
 static void skl_psr_setup_su_vsc(struct intel_dp *intel_dp)
 {
        struct edp_vsc_psr psr_vsc;
+       struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+       struct drm_device *dev = intel_dig_port->base.base.dev;
+       struct drm_i915_private *dev_priv = to_i915(dev);
 
        /* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */
        memset(&psr_vsc, 0, sizeof(psr_vsc));
        psr_vsc.sdp_header.HB0 = 0;
        psr_vsc.sdp_header.HB1 = 0x7;
-       psr_vsc.sdp_header.HB2 = 0x3;
-       psr_vsc.sdp_header.HB3 = 0xb;
+       if (dev_priv->psr.colorimetry_support &&
+               dev_priv->psr.y_cord_support) {
+               psr_vsc.sdp_header.HB2 = 0x5;
+               psr_vsc.sdp_header.HB3 = 0x13;
+       } else if (dev_priv->psr.y_cord_support) {
+               psr_vsc.sdp_header.HB2 = 0x4;
+               psr_vsc.sdp_header.HB3 = 0xe;
+       } else {
+               psr_vsc.sdp_header.HB2 = 0x3;
+               psr_vsc.sdp_header.HB3 = 0xc;
+       }
+
        intel_psr_write_vsc(intel_dp, &psr_vsc);
 }