drm/amdgpu/vcn4: replace ip based software ring decode with common vcn software ring...

Replace ip based software ring decode with common vcn software ring decode.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Christian Koenig <Christian.Koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
index dada3e3..c37dbac 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
@@ -29,7 +29,7 @@
 #include "soc15d.h"
 #include "soc15_hw_ip.h"
 #include "vcn_v2_0.h"
-#include "vcn_v3_0.h"
+#include "vcn_sw_ring.h"
 
 #include "vcn/vcn_4_0_0_offset.h"
 #include "vcn/vcn_4_0_0_sh_mask.h"
@@ -1490,22 +1490,20 @@ static const struct amdgpu_ring_funcs vcn_v4_0_dec_sw_ring_vm_funcs = {
        .emit_frame_size =
                SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
                SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
-               4 + /* vcn_v3_0_dec_sw_ring_emit_vm_flush */
-               5 + 5 + /* vcn_v3_0_dec_sw_ring_emit_fdec_swe x2 vm fdec_swe */
-               1, /* vcn_v3_0_dec_sw_ring_insert_end */
-       .emit_ib_size = 5, /* vcn_v3_0_dec_sw_ring_emit_ib */
-       .emit_ib = vcn_v3_0_dec_sw_ring_emit_ib,
-       .emit_fence = vcn_v3_0_dec_sw_ring_emit_fence,
-       .emit_vm_flush = vcn_v3_0_dec_sw_ring_emit_vm_flush,
+               VCN_SW_RING_EMIT_FRAME_SIZE,
+       .emit_ib_size = 5, /* vcn_dec_sw_ring_emit_ib */
+       .emit_ib = vcn_dec_sw_ring_emit_ib,
+       .emit_fence = vcn_dec_sw_ring_emit_fence,
+       .emit_vm_flush = vcn_dec_sw_ring_emit_vm_flush,
        .test_ring = amdgpu_vcn_dec_sw_ring_test_ring,
        .test_ib = amdgpu_vcn_dec_sw_ring_test_ib,
        .insert_nop = amdgpu_ring_insert_nop,
-       .insert_end = vcn_v3_0_dec_sw_ring_insert_end,
+       .insert_end = vcn_dec_sw_ring_insert_end,
        .pad_ib = amdgpu_ring_generic_pad_ib,
        .begin_use = amdgpu_vcn_ring_begin_use,
        .end_use = amdgpu_vcn_ring_end_use,
-       .emit_wreg = vcn_v3_0_dec_sw_ring_emit_wreg,
-       .emit_reg_wait = vcn_v3_0_dec_sw_ring_emit_reg_wait,
+       .emit_wreg = vcn_dec_sw_ring_emit_wreg,
+       .emit_reg_wait = vcn_dec_sw_ring_emit_reg_wait,
        .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
 };