pan/bi: Augment ST_TILE with register format

To model its Valhall incarnation.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15223>

diff --git a/src/panfrost/bifrost/ISA.xml b/src/panfrost/bifrost/ISA.xml
index c4a8c94..0232347 100644 (file)
--- a/src/panfrost/bifrost/ISA.xml
+++ b/src/panfrost/bifrost/ISA.xml
@@ -7709,6 +7709,12 @@
       <opt>v3</opt>
       <opt>v4</opt>
     </mod>
+    <mod name="register_format" size="3" pseudo="true">
+      <opt>f32</opt>
+      <opt>f16</opt>
+      <opt>u32</opt>
+      <opt>s32</opt>
+    </mod>
   </ins>
 
   <ins name="+SWZ.v2i16" mask="0xfffc8" exact="0x3d948">

diff --git a/src/panfrost/bifrost/bifrost_compile.c b/src/panfrost/bifrost/bifrost_compile.c
index fd7d2f1..d168648 100644 (file)
--- a/src/panfrost/bifrost/bifrost_compile.c
+++ b/src/panfrost/bifrost/bifrost_compile.c
@@ -523,7 +523,8 @@ bi_emit_blend_op(bi_builder *b, bi_index rgba, nir_alu_type T,
                 /* Conversion descriptor comes from the compile inputs, pixel
                  * indices derived at run time based on sample ID */
                 bi_st_tile(b, rgba, bi_pixel_indices(b, rt), bi_register(60),
-                                bi_imm_u32(blend_desc >> 32), BI_VECSIZE_V4);
+                                bi_imm_u32(blend_desc >> 32),
+                                regfmt, BI_VECSIZE_V4);
         } else if (b->shader->inputs->is_blend) {
                 /* Blend descriptor comes from the compile inputs */
                 /* Put the result in r0 */