riscv: dts: microchip: add sevkit device tree

Add a basic dts for the Microchip Smart Embedded Vision dev kit.
The SEV kit is an upcoming first party board, featuring an MPFS250T and:
- Dual Sony Camera Sensors (IMX334)
- IEEE 802.11 b/g/n 20MHz (1x1) Wi-Fi
- Bluetooth 5 Low Energy
- 4 GB DDR4 x64
- 2 GB LPDDR4 x32
- 1 GB SPI Flash
- 8 GB eMMC flash & SD card slot (multiplexed)
- HDMI2.0 Video Input/Output
- MIPI DSI Output
- MIPI CSI-2 Input

Link: https://onlinedocs.microchip.com/pr/GUID-404D3738-DC76-46BA-8683-6A77E837C2DD-en-US-1/index.html?GUID-065AEBEE-7B2C-4895-8579-B1D73D797F06
Signed-off-by: Vattipalli Praveen <praveen.kumar@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile
index 39aae7b..f18477b 100644 (file)
--- a/arch/riscv/boot/dts/microchip/Makefile
+++ b/arch/riscv/boot/dts/microchip/Makefile
@@ -1,4 +1,5 @@
 # SPDX-License-Identifier: GPL-2.0
 dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb
 dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-polarberry.dtb
+dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-sev-kit.dtb
 obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))

diff --git a/arch/riscv/boot/dts/microchip/mpfs-sev-kit-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-sev-kit-fabric.dtsi
new file mode 100644 (file)
index 0000000..8545baf
--- /dev/null
+++ b/arch/riscv/boot/dts/microchip/mpfs-sev-kit-fabric.dtsi
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2022 Microchip Technology Inc */
+
+/ {
+       fabric_clk3: fabric-clk3 {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <0>;
+       };
+
+       fabric_clk1: fabric-clk1 {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <125000000>;
+       };
+
+       pcie: pcie@2000000000 {
+               compatible = "microchip,pcie-host-1.0";
+               #address-cells = <0x3>;
+               #interrupt-cells = <0x1>;
+               #size-cells = <0x2>;
+               device_type = "pci";
+               reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
+               reg-names = "cfg", "apb";
+               bus-range = <0x0 0x7f>;
+               interrupt-parent = <&plic>;
+               interrupts = <119>;
+               interrupt-map = <0 0 0 1 &pcie_intc 0>,
+                               <0 0 0 2 &pcie_intc 1>,
+                               <0 0 0 3 &pcie_intc 2>,
+                               <0 0 0 4 &pcie_intc 3>;
+               interrupt-map-mask = <0 0 0 7>;
+               clocks = <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>;
+               clock-names = "fic0", "fic1", "fic3";
+               ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>;
+               msi-parent = <&pcie>;
+               msi-controller;
+               status = "disabled";
+               pcie_intc: interrupt-controller {
+                       #address-cells = <0>;
+                       #interrupt-cells = <1>;
+                       interrupt-controller;
+               };
+       };
+};

diff --git a/arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts
new file mode 100644 (file)
index 0000000..013cb66
--- /dev/null
+++ b/arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts
@@ -0,0 +1,145 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2022 Microchip Technology Inc */
+
+/dts-v1/;
+
+#include "mpfs.dtsi"
+#include "mpfs-sev-kit-fabric.dtsi"
+
+/* Clock frequency (in Hz) of the rtcclk */
+#define MTIMER_FREQ            1000000
+
+/ {
+       #address-cells = <2>;
+       #size-cells = <2>;
+       model = "Microchip PolarFire-SoC SEV Kit";
+       compatible = "microchip,mpfs-sev-kit", "microchip,mpfs";
+
+       aliases {
+               ethernet0 = &mac1;
+               serial0 = &mmuart0;
+               serial1 = &mmuart1;
+               serial2 = &mmuart2;
+               serial3 = &mmuart3;
+               serial4 = &mmuart4;
+       };
+
+       chosen {
+               stdout-path = "serial1:115200n8";
+       };
+
+       cpus {
+               timebase-frequency = <MTIMER_FREQ>;
+       };
+
+       reserved-memory {
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               fabricbuf0ddrc: buffer@80000000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x0 0x80000000 0x0 0x2000000>;
+               };
+
+               fabricbuf1ddrnc: buffer@c4000000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x0 0xc4000000 0x0 0x4000000>;
+               };
+
+               fabricbuf2ddrncwcb: buffer@d4000000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x0 0xd4000000 0x0 0x4000000>;
+               };
+       };
+
+       ddrc_cache: memory@1000000000 {
+               device_type = "memory";
+               reg = <0x10 0x0 0x0 0x76000000>;
+       };
+};
+
+&i2c0 {
+       status = "okay";
+};
+
+&gpio2 {
+       interrupts = <53>, <53>, <53>, <53>,
+                    <53>, <53>, <53>, <53>,
+                    <53>, <53>, <53>, <53>,
+                    <53>, <53>, <53>, <53>,
+                    <53>, <53>, <53>, <53>,
+                    <53>, <53>, <53>, <53>,
+                    <53>, <53>, <53>, <53>,
+                    <53>, <53>, <53>, <53>;
+       status = "okay";
+};
+
+&mac0 {
+       status = "okay";
+       phy-mode = "sgmii";
+       phy-handle = <&phy0>;
+       phy1: ethernet-phy@9 {
+               reg = <9>;
+       };
+       phy0: ethernet-phy@8 {
+               reg = <8>;
+       };
+};
+
+&mac1 {
+       status = "okay";
+       phy-mode = "sgmii";
+       phy-handle = <&phy1>;
+};
+
+&mbox {
+       status = "okay";
+};
+
+&mmc {
+       status = "okay";
+       bus-width = <4>;
+       disable-wp;
+       cap-sd-highspeed;
+       cap-mmc-highspeed;
+       mmc-ddr-1_8v;
+       mmc-hs200-1_8v;
+       sd-uhs-sdr12;
+       sd-uhs-sdr25;
+       sd-uhs-sdr50;
+       sd-uhs-sdr104;
+};
+
+&mmuart1 {
+       status = "okay";
+};
+
+&mmuart2 {
+       status = "okay";
+};
+
+&mmuart3 {
+       status = "okay";
+};
+
+&mmuart4 {
+       status = "okay";
+};
+
+&refclk {
+       clock-frequency = <125000000>;
+};
+
+&rtc {
+       status = "okay";
+};
+
+&syscontroller {
+       status = "okay";
+};
+
+&usb {
+       status = "okay";
+       dr_mode = "otg";
+};