static const uint8_t g_ppcle_opcode[] = {0x08, 0x00, 0xe0, 0x7f}; // trap
static const uint8_t g_riscv_opcode[] = {0x73, 0x00, 0x10, 0x00}; // ebreak
static const uint8_t g_riscv_opcode_c[] = {0x02, 0x90}; // c.ebreak
+ static const uint8_t g_loongarch_opcode[] = {0x05, 0x00, 0x2a,
+ 0x00}; // break 0x5
switch (GetArchitecture().GetMachine()) {
case llvm::Triple::aarch64:
: llvm::makeArrayRef(g_riscv_opcode);
}
+ case llvm::Triple::loongarch32:
+ case llvm::Triple::loongarch64:
+ return llvm::makeArrayRef(g_loongarch_opcode);
+
default:
return llvm::createStringError(llvm::inconvertibleErrorCode(),
"CPU type not supported!");
case llvm::Triple::ppc64le:
case llvm::Triple::riscv32:
case llvm::Triple::riscv64:
+ case llvm::Triple::loongarch32:
+ case llvm::Triple::loongarch64:
// On these architectures the PC doesn't get updated for breakpoint hits.
return 0;
}
} break;
+ case llvm::Triple::loongarch32:
+ case llvm::Triple::loongarch64: {
+ static const uint8_t g_loongarch_opcode[] = {0x05, 0x00, 0x2a,
+ 0x00}; // break 0x5
+ trap_opcode = g_loongarch_opcode;
+ trap_opcode_size = sizeof(g_loongarch_opcode);
+ } break;
+
default:
return 0;
}