bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset, unsigned num_registers,
uint32_t *out);
+
+ /**
+ * Secure context
+ */
+ bool (*ws_is_secure)(struct radeon_winsys *ws);
+ bool (*cs_is_secure)(struct radeon_cmdbuf *cs);
+ void (*cs_set_secure)(struct radeon_cmdbuf *cs, bool secure);
};
static inline bool radeon_emitted(struct radeon_cmdbuf *cs, unsigned num_dw)
/* the error returned from cs_flush for non-async submissions */
int error_code;
+
+ /* TMZ: will this command be submitted using the TMZ flag */
+ bool secure;
};
struct amdgpu_cs {
return a == b;
}
+static bool amdgpu_ws_is_secure(struct radeon_winsys *rws)
+{
+ struct amdgpu_winsys *ws = amdgpu_winsys(rws);
+ return ws->secure;
+}
+
+static bool amdgpu_cs_is_secure(struct radeon_cmdbuf *rcs)
+{
+ struct amdgpu_cs *cs = amdgpu_cs(rcs);
+ return cs->csc->secure;
+}
+
+static void amdgpu_cs_set_secure(struct radeon_cmdbuf *rcs, bool secure)
+{
+ struct amdgpu_cs *cs = amdgpu_cs(rcs);
+ cs->csc->secure = secure;
+}
+
PUBLIC struct radeon_winsys *
amdgpu_winsys_create(int fd, const struct pipe_screen_config *config,
radeon_screen_create_t screen_create)
ws->base.query_value = amdgpu_query_value;
ws->base.read_registers = amdgpu_read_registers;
ws->base.pin_threads_to_L3_cache = amdgpu_pin_threads_to_L3_cache;
+ ws->base.ws_is_secure = amdgpu_ws_is_secure;
+ ws->base.cs_is_secure = amdgpu_cs_is_secure;
+ ws->base.cs_set_secure = amdgpu_cs_set_secure;
amdgpu_bo_init_functions(ws);
amdgpu_cs_init_functions(ws);
bool debug_all_bos;
bool reserve_vmid;
bool zero_all_vram_allocs;
+ bool secure;
/* List of all allocated buffers */
simple_mtx_t global_bo_list_lock;
}
}
+static bool radeon_ws_is_secure(struct radeon_winsys* ws)
+{
+ return false;
+}
+
+static bool radeon_cs_is_secure(struct radeon_cmdbuf* cs)
+{
+ return false;
+}
+
+static void radeon_cs_set_secure(struct radeon_cmdbuf* cs, bool enable)
+{
+}
+
PUBLIC struct radeon_winsys *
radeon_drm_winsys_create(int fd, const struct pipe_screen_config *config,
radeon_screen_create_t screen_create)
ws->base.cs_request_feature = radeon_cs_request_feature;
ws->base.query_value = radeon_query_value;
ws->base.read_registers = radeon_read_registers;
+ ws->base.ws_is_secure = radeon_ws_is_secure;
+ ws->base.cs_is_secure = radeon_cs_is_secure;
+ ws->base.cs_set_secure = radeon_cs_set_secure;
radeon_drm_bo_init_functions(ws);
radeon_drm_cs_init_functions(ws);