[PowerPC] Don't use the S30 and S31 regs for the pic code

These changes to address issue
https://github.com/llvm/llvm-project/issues/55857.

Since R30/S30 is used as pointer (32 bits) for GOT Table in the ppc32 ABI,
remove it from the SPE callee save register when PIC is enabled.

This prevents emitting the SPE load and store for S30 and S31 regs.

Differential revision: https://reviews.llvm.org/D127495

diff --git a/llvm/lib/Target/PowerPC/PPCCallingConv.td b/llvm/lib/Target/PowerPC/PPCCallingConv.td
index 3df3177..8f9dc98 100644 (file)
--- a/llvm/lib/Target/PowerPC/PPCCallingConv.td
+++ b/llvm/lib/Target/PowerPC/PPCCallingConv.td
@@ -272,13 +272,19 @@ def CSR_SVR432 :  CalleeSavedRegs<(add CSR_SVR432_COMM, F14, F15, F16, F17, F18,
                                         F27, F28, F29, F30, F31
                                    )>;
 def CSR_SPE : CalleeSavedRegs<(add S14, S15, S16, S17, S18, S19, S20, S21, S22,
-                                   S23, S24, S25, S26, S27, S28, S29, S30, S31
+                                   S23, S24, S25, S26, S27, S28, S29, S30 
                               )>;
 
+def CSR_SPE_NO_S30_31 : CalleeSavedRegs<(add S14, S15, S16, S17, S18, S19, S20, S21,
+                                         S22, S23, S24, S25, S26, S27, S28, S29
+                             )>;
+
 def CSR_SVR432_Altivec : CalleeSavedRegs<(add CSR_SVR432, CSR_Altivec)>;
 
 def CSR_SVR432_SPE : CalleeSavedRegs<(add CSR_SVR432_COMM, CSR_SPE)>;
 
+def CSR_SVR432_SPE_NO_S30_31 : CalleeSavedRegs<(add CSR_SVR432_COMM, CSR_SPE_NO_S30_31)>;
+
 def CSR_AIX32 : CalleeSavedRegs<(add R13, R14, R15, R16, R17, R18, R19, R20,
                                      R21, R22, R23, R24, R25, R26, R27, R28,
                                      R29, R30, R31, F14, F15, F16, F17, F18,

diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
index 7349eb8..5ab1043 100644 (file)
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -257,8 +257,11 @@ PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
     return CSR_SVR432_VSRP_SaveList;
   if (Subtarget.hasAltivec())
     return CSR_SVR432_Altivec_SaveList;
-  else if (Subtarget.hasSPE())
+  else if (Subtarget.hasSPE()) {
+    if (TM.isPositionIndependent() && !TM.isPPC64())
+      return CSR_SVR432_SPE_NO_S30_31_SaveList;
     return CSR_SVR432_SPE_SaveList;
+   }
   return CSR_SVR432_SaveList;
 }
 
@@ -317,8 +320,11 @@ PPCRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
                ? CSR_SVR432_VSRP_RegMask
                : (Subtarget.hasAltivec()
                       ? CSR_SVR432_Altivec_RegMask
-                      : (Subtarget.hasSPE() ? CSR_SVR432_SPE_RegMask
-                                            : CSR_SVR432_RegMask));
+                      : (Subtarget.hasSPE()
+                             ? (TM.isPositionIndependent()
+                                     ? CSR_SVR432_SPE_NO_S30_31_RegMask
+                                     : CSR_SVR432_SPE_RegMask)
+                             : CSR_SVR432_RegMask));
 }
 
 const uint32_t*

diff --git a/llvm/test/CodeGen/PowerPC/pr55857.ll b/llvm/test/CodeGen/PowerPC/pr55857.ll
new file mode 100644 (file)
index 0000000..ae86c39
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/pr55857.ll
@@ -0,0 +1,18 @@
+; RUN: llc --relocation-model=pic  \
+; RUN:   -mtriple=ppc32 < %s | FileCheck  %s 
+
+@g = global i32 10, align 4
+
+; Function Attrs: noinline nounwind optnone uwtable
+define i32 @main() #0 {
+; CHECK-LABEL: main:
+; CHECK-NOT: evstdd
+entry:
+  %retval = alloca i32, align 4
+  store i32 0, ptr %retval, align 4
+  %0 = load i32, ptr @g, align 4
+  ret i32 %0
+}
+
+attributes #0 = { noinline nounwind optnone uwtable "frame-pointer"="all" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="e500" "target-features"="+spe,-altivec,-bpermd,-crbits,-crypto,-direct-move,-extdiv,-htm,-isa-v206-instructions,-isa-v207-instructions,-isa-v30-instructions,-power8-vector,-power9-vector,-privileged,-quadword-atomics,-rop-protect,-vsx" }
+

diff --git a/llvm/test/CodeGen/PowerPC/spe.ll b/llvm/test/CodeGen/PowerPC/spe.ll
index 4598e79..0a23453 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/spe.ll
+++ b/llvm/test/CodeGen/PowerPC/spe.ll
@@ -1639,14 +1639,13 @@ define double @test_spill(double %a, i32 %a1, i64 %a2, i8 * %a3, i32 *%a4, i32*
 ; SPE:       # %bb.0: # %entry
 ; SPE-NEXT:    mflr 0
 ; SPE-NEXT:    stw 0, 4(1)
-; SPE-NEXT:    stwu 1, -272(1)
+; SPE-NEXT:    stwu 1, -288(1)
 ; SPE-NEXT:    li 5, 256
-; SPE-NEXT:    evstddx 30, 1, 5 # 8-byte Folded Spill
-; SPE-NEXT:    li 5, 264
-; SPE-NEXT:    evstddx 31, 1, 5 # 8-byte Folded Spill
-; SPE-NEXT:    li 5, .LCPI55_0@l
+; SPE-NEXT:    evstddx 30, 1, 5  # 8-byte Folded Spill
+; SPE-NEXT:    li 5, .LCPI55_0@
 ; SPE-NEXT:    lis 6, .LCPI55_0@ha
 ; SPE-NEXT:    evlddx 5, 6, 5
+; SPE-NEXT:    stw 31, 284(1)    # 4-byte Folded Spill
 ; SPE-NEXT:    evstdd 14, 128(1) # 8-byte Folded Spill
 ; SPE-NEXT:    evstdd 15, 136(1) # 8-byte Folded Spill
 ; SPE-NEXT:    evstdd 16, 144(1) # 8-byte Folded Spill
@@ -1664,7 +1663,7 @@ define double @test_spill(double %a, i32 %a1, i64 %a2, i8 * %a3, i32 *%a4, i32*
 ; SPE-NEXT:    evstdd 28, 240(1) # 8-byte Folded Spill
 ; SPE-NEXT:    evstdd 29, 248(1) # 8-byte Folded Spill
 ; SPE-NEXT:    evmergelo 3, 3, 4
-; SPE-NEXT:    lwz 4, 280(1)
+; SPE-NEXT:    lwz 4, 296(1)
 ; SPE-NEXT:    efdadd 3, 3, 3
 ; SPE-NEXT:    efdadd 3, 3, 5
 ; SPE-NEXT:    evstdd 3, 24(1) # 8-byte Folded Spill
@@ -1686,13 +1685,11 @@ define double @test_spill(double %a, i32 %a1, i64 %a2, i8 * %a3, i32 *%a4, i32*
 ; SPE-NEXT:    li 6, 1
 ; SPE-NEXT:    bl test_memset
 ; SPE-NEXT:    evldd 4, 24(1) # 8-byte Folded Reload
-; SPE-NEXT:    li 5, 264
-; SPE-NEXT:    evmergehi 3, 4, 4
-; SPE-NEXT:    evlddx 31, 1, 5 # 8-byte Folded Reload
 ; SPE-NEXT:    li 5, 256
-; SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
+; SPE-NEXT:    evmergehi 3, 4, 4
 ; SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
 ; SPE-NEXT:    evlddx 30, 1, 5 # 8-byte Folded Reload
+; SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
 ; SPE-NEXT:    evldd 29, 248(1) # 8-byte Folded Reload
 ; SPE-NEXT:    evldd 28, 240(1) # 8-byte Folded Reload
 ; SPE-NEXT:    evldd 27, 232(1) # 8-byte Folded Reload
@@ -1709,8 +1706,9 @@ define double @test_spill(double %a, i32 %a1, i64 %a2, i8 * %a3, i32 *%a4, i32*
 ; SPE-NEXT:    evldd 16, 144(1) # 8-byte Folded Reload
 ; SPE-NEXT:    evldd 15, 136(1) # 8-byte Folded Reload
 ; SPE-NEXT:    evldd 14, 128(1) # 8-byte Folded Reload
-; SPE-NEXT:    lwz 0, 276(1)
-; SPE-NEXT:    addi 1, 1, 272
+; SPE-NEXT:    lwz 31, 284(1)   # 4-byte Folded Reload
+; SPE-NEXT:    lwz 0, 292(1)
+; SPE-NEXT:    addi 1, 1, 288
 ; SPE-NEXT:    mtlr 0
 ; SPE-NEXT:    blr
 ;