Convert CONFIG_SYS_SRIO et al to Kconfig
authorTom Rini <trini@konsulko.com>
Wed, 16 Nov 2022 18:10:39 +0000 (13:10 -0500)
committerTom Rini <trini@konsulko.com>
Mon, 5 Dec 2022 21:06:07 +0000 (16:06 -0500)
This converts the following to Kconfig:
   CONFIG_SRIO1
   CONFIG_SRIO2
   CONFIG_SRIO_PCIE_BOOT_MASTER
   CONFIG_SYS_SRIO

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
20 files changed:
README
arch/powerpc/Kconfig
configs/MPC8548CDS_36BIT_defconfig
configs/MPC8548CDS_defconfig
configs/MPC8548CDS_legacy_defconfig
configs/P2041RDB_NAND_defconfig
configs/P2041RDB_SDCARD_defconfig
configs/P2041RDB_SPIFLASH_defconfig
configs/P2041RDB_defconfig
configs/T2080QDS_NAND_defconfig
configs/T2080QDS_SDCARD_defconfig
configs/T2080QDS_SECURE_BOOT_defconfig
configs/T2080QDS_SPIFLASH_defconfig
configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
configs/T2080QDS_defconfig
include/configs/MPC8548CDS.h
include/configs/P2041RDB.h
include/configs/T102xRDB.h
include/configs/T208xQDS.h
include/configs/T208xRDB.h

diff --git a/README b/README
index b095937..bb35a89 100644 (file)
--- a/README
+++ b/README
@@ -1686,18 +1686,6 @@ Low Level (hardware related) configuration options:
 - CONFIG_SYS_OR_TIMING_SDRAM:
                SDRAM timing
 
-- CONFIG_SYS_SRIO:
-               Chip has SRIO or not
-
-- CONFIG_SRIO1:
-               Board has SRIO 1 port available
-
-- CONFIG_SRIO2:
-               Board has SRIO 2 port available
-
-- CONFIG_SRIO_PCIE_BOOT_MASTER
-               Board can support master function for Boot from SRIO and PCIE
-
 - CONFIG_SYS_SRIOn_MEM_VIRT:
                Virtual Address of SRIO port 'n' memory region
 
index c355a95..cf93a7b 100644 (file)
@@ -44,6 +44,21 @@ config SYS_INIT_RAM_LOCK
        bool "Lock some portion of L1 for initial ram stack"
        depends on MPC83xx || MPC85xx
 
+config SYS_SRIO
+       bool "Serial RapidIO support"
+
+config SRIO1
+       bool "Board has SRIO 1 port available"
+       depends on SYS_SRIO
+
+config SRIO2
+       bool "Board has SRIO 2 port available"
+       depends on SYS_SRIO
+
+config SRIO_PCIE_BOOT_MASTER
+       bool "Board can support master function for Boot from SRIO and PCIE"
+       depends on SYS_SRIO
+
 source "arch/powerpc/cpu/mpc83xx/Kconfig"
 source "arch/powerpc/cpu/mpc85xx/Kconfig"
 source "arch/powerpc/cpu/mpc8xx/Kconfig"
index 85b055a..86a67d7 100644 (file)
@@ -8,6 +8,8 @@ CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds_36b"
 CONFIG_ENV_ADDR=0xFFF60000
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y
+CONFIG_SYS_SRIO=y
+CONFIG_SRIO1=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_MPC8548CDS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
index 0d21b89..2ac4f26 100644 (file)
@@ -8,6 +8,8 @@ CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds"
 CONFIG_ENV_ADDR=0xFFF60000
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y
+CONFIG_SYS_SRIO=y
+CONFIG_SRIO1=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_MPC8548CDS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
index b01919e..faabd7b 100644 (file)
@@ -8,6 +8,8 @@ CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds"
 CONFIG_ENV_ADDR=0xFFF60000
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y
+CONFIG_SYS_SRIO=y
+CONFIG_SRIO1=y
 # CONFIG_CMD_ERRATA is not set
 CONFIG_TARGET_MPC8548CDS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
index 0eec508..3d24b1a 100644 (file)
@@ -6,6 +6,10 @@ CONFIG_ENV_OFFSET=0xE0000
 CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y
+CONFIG_SYS_SRIO=y
+CONFIG_SRIO1=y
+CONFIG_SRIO2=y
+CONFIG_SRIO_PCIE_BOOT_MASTER=y
 CONFIG_TARGET_P2041RDB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
index f9f4c31..cec55a1 100644 (file)
@@ -6,6 +6,10 @@ CONFIG_ENV_OFFSET=0xCF400
 CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y
+CONFIG_SYS_SRIO=y
+CONFIG_SRIO1=y
+CONFIG_SRIO2=y
+CONFIG_SRIO_PCIE_BOOT_MASTER=y
 CONFIG_TARGET_P2041RDB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
index 6a97437..5fcf154 100644 (file)
@@ -7,6 +7,10 @@ CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y
+CONFIG_SYS_SRIO=y
+CONFIG_SRIO1=y
+CONFIG_SRIO2=y
+CONFIG_SRIO_PCIE_BOOT_MASTER=y
 CONFIG_TARGET_P2041RDB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
index 1725a8a..ce198e2 100644 (file)
@@ -7,6 +7,10 @@ CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
 CONFIG_ENV_ADDR=0xEFF20000
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y
+CONFIG_SYS_SRIO=y
+CONFIG_SRIO1=y
+CONFIG_SRIO2=y
+CONFIG_SRIO_PCIE_BOOT_MASTER=y
 CONFIG_TARGET_P2041RDB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
index dd7473e..637842c 100644 (file)
@@ -11,6 +11,10 @@ CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y
+CONFIG_SYS_SRIO=y
+CONFIG_SRIO1=y
+CONFIG_SRIO2=y
+CONFIG_SRIO_PCIE_BOOT_MASTER=y
 CONFIG_TARGET_T2080QDS=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
index 364aab5..35ab993 100644 (file)
@@ -12,6 +12,10 @@ CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y
+CONFIG_SYS_SRIO=y
+CONFIG_SRIO1=y
+CONFIG_SRIO2=y
+CONFIG_SRIO_PCIE_BOOT_MASTER=y
 CONFIG_TARGET_T2080QDS=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
index c6710a0..93b02a5 100644 (file)
@@ -4,6 +4,10 @@ CONFIG_ENV_SIZE=0x2000
 CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y
+CONFIG_SYS_SRIO=y
+CONFIG_SRIO1=y
+CONFIG_SRIO2=y
+CONFIG_SRIO_PCIE_BOOT_MASTER=y
 CONFIG_TARGET_T2080QDS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
index a705542..7d25bbb 100644 (file)
@@ -14,6 +14,10 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y
+CONFIG_SYS_SRIO=y
+CONFIG_SRIO1=y
+CONFIG_SRIO2=y
+CONFIG_SRIO_PCIE_BOOT_MASTER=y
 CONFIG_TARGET_T2080QDS=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
index d6d6ec0..2846f63 100644 (file)
@@ -5,6 +5,10 @@ CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
 CONFIG_ENV_ADDR=0xFFE20000
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y
+CONFIG_SYS_SRIO=y
+CONFIG_SRIO1=y
+CONFIG_SRIO2=y
+CONFIG_SRIO_PCIE_BOOT_MASTER=y
 CONFIG_TARGET_T2080QDS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
index 802213d..a7dc88c 100644 (file)
@@ -6,6 +6,10 @@ CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
 CONFIG_ENV_ADDR=0xEFF20000
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y
+CONFIG_SYS_SRIO=y
+CONFIG_SRIO1=y
+CONFIG_SRIO2=y
+CONFIG_SRIO_PCIE_BOOT_MASTER=y
 CONFIG_TARGET_T2080QDS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
index 6a51149..eb75f8b 100644 (file)
@@ -13,9 +13,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_SYS_SRIO
-#define CONFIG_SRIO1                   /* SRIO port 1 */
-
 #define CONFIG_INTERRUPTS              /* enable pci, srio, ddr interrupts */
 
 #ifndef __ASSEMBLY__
index d7e06d2..be8d09f 100644 (file)
 
 #define CFG_SYS_NUM_CPC                CONFIG_SYS_NUM_DDR_CTLRS
 
-#define CONFIG_SYS_SRIO
-#define CONFIG_SRIO1                   /* SRIO port 1 */
-#define CONFIG_SRIO2                   /* SRIO port 2 */
-#define CONFIG_SRIO_PCIE_BOOT_MASTER
-
 #ifndef __ASSEMBLY__
 #include <linux/stringify.h>
 #endif
index 616387f..f9f9318 100644 (file)
@@ -49,8 +49,6 @@
 #define CONFIG_RESET_VECTOR_ADDRESS    0xeffffffc
 #endif
 
-/* PCIe Boot - Master */
-#define CONFIG_SRIO_PCIE_BOOT_MASTER
 /*
  * for slave u-boot IMAGE instored in master memory space,
  * PHYS must be aligned based on the SIZE
index 8f56de4..acaad1b 100644 (file)
 #include <linux/stringify.h>
 
 #define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
-#if defined(CONFIG_ARCH_T2080)
-#define CONFIG_SYS_SRIO                /* Enable Serial RapidIO Support */
-#define CONFIG_SRIO1           /* SRIO port 1 */
-#define CONFIG_SRIO2           /* SRIO port 2 */
-#endif
 
 /* High Level Configuration Options */
 
@@ -52,7 +47,6 @@
 
 #endif /* CONFIG_RAMBOOT_PBL */
 
-#define CONFIG_SRIO_PCIE_BOOT_MASTER
 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 /* Set 1M boot space */
 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
index e9db4a2..7315afa 100644 (file)
@@ -47,7 +47,6 @@
 
 #endif /* CONFIG_RAMBOOT_PBL */
 
-#define CONFIG_SRIO_PCIE_BOOT_MASTER
 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 /* Set 1M boot space */
 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)