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AMDGPU/GlobalISel: Add SReg_96 to SGPRRegBank
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Sun, 26 Jul 2020 15:04:37 +0000 (11:04 -0400)
committerMatt Arsenault <Matthew.Arsenault@amd.com>
Tue, 28 Jul 2020 20:49:55 +0000 (16:49 -0400)
llvm/lib/Target/AMDGPU/AMDGPURegisterBanks.td patch | blob | history

diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBanks.td b/llvm/lib/Target/AMDGPU/AMDGPURegisterBanks.td
index 9f6ebd0..6c70b53 100644 (file)
--- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBanks.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBanks.td
@@ -7,7 +7,7 @@
 //===----------------------------------------------------------------------===//
 
 def SGPRRegBank : RegisterBank<"SGPR",
-  [SReg_LO16, SReg_32, SReg_64, SReg_128, SReg_160, SReg_192, SReg_256, SReg_512, SReg_1024]
+  [SReg_LO16, SReg_32, SReg_64, SReg_96, SReg_128, SReg_160, SReg_192, SReg_256, SReg_512, SReg_1024]
 >;
 
 def VGPRRegBank : RegisterBank<"VGPR",
Domain: System / Toolchain;