reg:
minItems: 2
- maxItems: 3
items:
- description: AHCI registers
- description: SATA configuration and IPFS registers
clocks:
minItems: 2
- maxItems: 4
items:
- description: High Frequency Oscillator (usually at 24MHz)
- description: Low Frequency Oscillator (usually at 32kHz)
clock-names:
minItems: 2
- maxItems: 4
items:
- const: hosc
- const: losc
nvmem-cell-names:
minItems: 1
- maxItems: 2
items:
- const: calib
- const: calib_backup
- description: Sleep clock source
- description: PLL test clock source (Optional clock)
minItems: 2
- maxItems: 3
clock-names:
items:
- const: sleep_clk
- const: core_bi_pll_test_se # Optional clock
minItems: 2
- maxItems: 3
'#clock-cells':
const: 1
- description: USB3 phy wrapper pipe clock source (Optional clock)
- description: USB3 phy sec pipe clock source (Optional clock)
minItems: 2
- maxItems: 13
clock-names:
items:
- const: usb3_phy_wrapper_gcc_usb30_pipe_clk # Optional clock
- const: usb3_uni_phy_sec_gcc_usb30_pipe_clk # Optional clock
minItems: 2
- maxItems: 13
'#clock-cells':
const: 1
clock-names:
minItems: 1
- maxItems: 4
items:
- const: ext-26m
- const: ext-32k
- description: Module clock
- description: MBus clock
minItems: 2
- maxItems: 3
clock-names:
items:
- const: mod
- const: ram
minItems: 2
- maxItems: 3
resets:
maxItems: 1
- description: MXS DCP DCP interrupt
- description: MXS DCP secure interrupt
minItems: 2
- maxItems: 3
clocks:
maxItems: 1
reg:
minItems: 1
- maxItems: 2
items:
- description: Display Backend registers
- description: SAT registers
reg-names:
minItems: 1
- maxItems: 2
items:
- const: be
- const: sat
clocks:
minItems: 3
- maxItems: 4
items:
- description: The backend interface clock
- description: The backend module clock
clock-names:
minItems: 3
- maxItems: 4
items:
- const: ahb
- const: mod
resets:
minItems: 1
- maxItems: 2
items:
- description: The Backend reset line
- description: The SAT reset line
reset-names:
minItems: 1
- maxItems: 2
items:
- const: be
- const: sat
clocks:
minItems: 1
- maxItems: 2
items:
- description: Bus Clock
- description: Module Clock
clocks:
minItems: 3
- maxItems: 6
items:
- description: Bus Clock
- description: Register Clock
clock-names:
minItems: 3
- maxItems: 6
items:
- const: iahb
- const: isfr
resets:
minItems: 1
- maxItems: 2
items:
- description: HDMI Controller Reset
- description: HDCP Reset
reset-names:
minItems: 1
- maxItems: 2
items:
- const: ctrl
- const: hdcp
clocks:
minItems: 2
- maxItems: 4
items:
- description: Bus Clock
- description: Module Clock
clock-names:
minItems: 2
- maxItems: 4
items:
- const: bus
- const: mod
clocks:
minItems: 2
- maxItems: 6
items:
- description: The TCON TOP interface clock
- description: The TCON TOP TV0 clock
clock-names:
minItems: 2
- maxItems: 6
items:
- const: bus
- const: tcon-tv0
Names of maps with programmable addresses. It can contain any map
needing a non-default address.
minItems: 1
- maxItems: 4
items:
- const: main
- const: edid
reg:
minItems: 1
- maxItems: 2
items:
- description:
Register block of mhdptx apb registers up to PHY mapped area (AUX_CONFIG_P).
reg-names:
minItems: 1
- maxItems: 2
items:
- const: mhdptx
- const: j721e-intg
clocks:
minItems: 2
- maxItems: 5
items:
- {}
- {}
clock-names:
minItems: 2
- maxItems: 5
items:
- {}
- {}
- description: DSI bus clock
- description: Pixel clock
minItems: 2
- maxItems: 3
clock-names:
items:
- const: ref
- const: px_clk
minItems: 2
- maxItems: 3
resets:
maxItems: 1
- description: events interrupt line.
- description: errors interrupt line.
minItems: 1
- maxItems: 2
clocks:
maxItems: 1
The APB clock and at least one video clock are mandatory, the audio clock
is optional.
minItems: 2
- maxItems: 4
items:
- description: dp_apb_clk is the APB clock
- description: dp_aud_clk is the Audio clock
clock-names:
oneOf:
- minItems: 2
- maxItems: 3
items:
- const: dp_apb_clk
- enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ]
- enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ]
- minItems: 3
- maxItems: 4
items:
- const: dp_apb_clk
- const: dp_aud_clk
maxItems: 2
phy-names:
minItems: 1
- maxItems: 2
items:
- const: dp-phy0
- const: dp-phy1
interrupt-names:
minItems: 9
- maxItems: 17
items:
- const: error
- pattern: "^ch([0-9]|1[0-5])$"
interrupts:
minItems: 1
- maxItems: 2
items:
- description: uncorrectable error interrupt
- description: correctable error interrupt
interrupt-names:
minItems: 1
- maxItems: 2
items:
- const: ue
- const: ce
oneOf:
- allOf:
- minItems: 1
- maxItems: 2
items:
- pattern: "^(atmel|catalyst|microchip|nxp|ramtron|renesas|rohm|st),(24(c|cs|lc|mac)[0-9]+|spd)$"
- pattern: "^atmel,(24(c|cs|mac)[0-9]+|spd)$"
interrupts:
# Either 1 or 2 interrupts can be present
minItems: 1
- maxItems: 2
items:
- description: tx or combined interrupt
- description: rx interrupt
interrupt-names:
# minItems must be specified here because the default would be 2
minItems: 1
- maxItems: 2
items:
- const: tx irq
- const: rx irq
- enum: [ bridge, gca ]
- enum: [ bridge, gca ]
minItems: 2
- maxItems: 4
interrupts:
items:
- description: AHB/slave interface clock (only required if GPU can gate
slave interface independently)
minItems: 1
- maxItems: 4
clock-names:
items:
reg:
minItems: 1
- maxItems: 2
items:
- description: address offset and range of bus
- description: address offset and range of bus buffer
reg:
minItems: 1
- maxItems: 2
items:
- description: BSC register range
- description: Auto-I2C register range
clocks:
minItems: 1
- maxItems: 2
items:
- description: Reference clock for the I2C bus
- description: Bus clock (Only for Armada 7K/8K)
clock-names:
minItems: 1
- maxItems: 2
items:
- const: core
- const: reg
reg:
minItems: 3
- maxItems: 4
items:
- description: Smbus block registers
- description: Cause master registers
clock-names:
minItems: 2
- maxItems: 4
items:
- const: clkin
- const: core
dfsdm clock can also feed CLKOUT, when CLKOUT is used.
- description: audio clock can be used as an alternate to feed CLKOUT.
minItems: 1
- maxItems: 2
clock-names:
items:
- const: dfsdm
- const: audio
minItems: 1
- maxItems: 2
"#address-cells":
const: 1
- description: output interrupt 6
- description: output interrupt 7
minItems: 1
- maxItems: 8
clocks:
maxItems: 1
- const: int2
- const: int3
minItems: 1
- maxItems: 4
'#interrupt-cells':
const: 2
If provided, then the combined interrupt will be used in preference to
any others.
- minItems: 2
- maxItems: 4
items:
- const: eventq # Event Queue not empty
- const: gerror # Global Error activated
interrupts:
minItems: 1
- maxItems: 2
description:
Specifiers for the MMU fault interrupts. Not required for cache IPMMUs.
items:
- description: tx channel free
- description: wakeup source
minItems: 2
- maxItems: 3
interrupt-names:
items:
- const: tx
- const: wakeup
minItems: 2
- maxItems: 3
wakeup-source: true
clock-names:
minItems: 4
- maxItems: 5
items:
- const: dos_parser
- const: dos
reg-names:
minItems: 1
- maxItems: 13
items:
- const: main
- enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ]
clocks:
minItems: 1
- maxItems: 3
items:
- description: AXI bus interface clock
- description: Peripheral clock
power-domain-names:
minItems: 2
- maxItems: 3
items:
- const: venus
- const: vcodec0
power-domain-names:
minItems: 3
- maxItems: 4
items:
- const: venus
- const: vcodec0
power-domain-names:
minItems: 2
- maxItems: 3
items:
- const: venus
- const: vcodec0
maxItems: 1
clock-names:
- maxItems: 1
items:
- const: fck
dma-names:
minItems: 1
- maxItems: 2
items:
- const: rx
- const: rx
apb and smi are mandatory. the async is only for generation 1 smi HW.
gals(global async local sync) also is optional, see below.
minItems: 2
- maxItems: 4
items:
- description: apb is Advanced Peripheral Bus clock, It's the clock for
setting the register.
- description: smi is the clock for transfer data and command.
- - description: async is asynchronous clock, it help transform the smi
- clock into the emi clock domain.
- - description: gals0 is the path0 clock of gals.
+ - description: Either asynchronous clock to help transform the smi clock
+ into the emi clock domain on Gen1 h/w, or the path0 clock of gals.
- description: gals1 is the path1 clock of gals.
clock-names:
description: |
apb and smi are mandatory. gals(global async local sync) is optional.
minItems: 2
- maxItems: 3
items:
- description: apb is Advanced Peripheral Bus clock, It's the clock for
setting the register.
clocks:
minItems: 2
- maxItems: 4
items:
- description: Bus Clock
- description: Module Clock
clock-names:
minItems: 2
- maxItems: 4
items:
- const: ahb
- const: mmc
pinctrl-names:
minItems: 1
- maxItems: 4
items:
- const: default
- const: state_100mhz
description:
Should contain phandle for the clock feeding the MMC controller.
minItems: 2
- maxItems: 8
items:
- description: source clock (required).
- description: HCLK which used for host (required).
clock-names:
minItems: 2
- maxItems: 8
items:
- const: source
- const: hclk
clock-names:
minItems: 1
- maxItems: 2
items:
- const: core
- const: cd
pinctrl-names:
minItems: 1
- maxItems: 2
items:
- const: default
- const: state_uhs
clock-names:
minItems: 1
- maxItems: 2
items:
- const: clk_ahb
- const: clk_xin
clock-names:
minItems: 1
- maxItems: 2
items:
- const: io
- const: core
properties:
clocks:
minItems: 3
- maxItems: 4
items:
- description: GMAC main clock
- description: First parent clock of the internal mux
clock-names:
minItems: 3
- maxItems: 4
items:
- const: stmmaceth
- const: clkin0
interrupts:
minItems: 1
- maxItems: 2
items:
- description: RX interrupt
- description: TX interrupt
interrupt-names:
minItems: 1
- maxItems: 2
items:
- const: rx
- const: tx
- description: interrupt line0
- description: interrupt line1
minItems: 1
- maxItems: 2
interrupt-names:
items:
- const: int0
- const: int1
minItems: 1
- maxItems: 2
clocks:
items:
clocks:
minItems: 1
- maxItems: 2
items:
- description: switch's main clock
- description: dividing of the switch core clock
clock-names:
minItems: 1
- maxItems: 2
items:
- const: sw_switch
- const: sw_switch_mdiv
gpios:
minItems: 2
- maxItems: 3
items:
- description: MDC
- description: MDIO
interrupts:
minItems: 1
- maxItems: 3
items:
- description: Combined signal for various interrupt events
- description: The interrupt to manage the remote wake-up packet detection
interrupt-names:
minItems: 1
- maxItems: 3
items:
- const: macirq
- const: eth_wake_irq
clocks:
minItems: 3
- maxItems: 5
items:
- description: GMAC main clock
- description: MAC TX clock
interrupts:
minItems: 1
- maxItems: 2
items:
- description: PCIe host controller
- description: builtin MSI controller
interrupt-names:
minItems: 1
- maxItems: 2
items:
- const: pcie
- const: msi
reg:
minItems: 1
- maxItems: 2
items:
- description: CFG0 standard config space register
- description: CFG1 extended config space register
reset-names:
minItems: 1
- maxItems: 2
items:
- const: phy
- const: mac
interrupts:
minItems: 1
- maxItems: 2
items:
- description: PCIe host controller
- description: builtin MSI controller
interrupt-names:
minItems: 1
- maxItems: 2
items:
- const: pcie
- const: msi
interrupts:
minItems: 1
- maxItems: 4
items:
- description: Overflow interrupt for DTC0
- description: Overflow interrupt for DTC1
clock-names:
minItems: 1
- maxItems: 2
items:
- const: usbh
- const: usb_ref
reg:
minItems: 1
- maxItems: 6
items:
- description: the base CTRL register
- description: XHCI EC register
reg-names:
minItems: 1
- maxItems: 6
items:
- const: ctrl
- const: xhci_ec
clock-names:
minItems: 1
- maxItems: 2
items:
- const: sw_usb
- const: sw_usb3
reg-names:
minItems: 1
- maxItems: 2
items:
- const: phy
- const: phy-ctrl
clocks:
minItems: 1
- maxItems: 2
items:
- description: Reference clock, (HS is 48Mhz, SS/P is 24~27Mhz)
- description: Reference clock of analog phy
clock-names:
minItems: 1
- maxItems: 2
items:
- const: ref
- const: da_ref
resets:
minItems: 1
- maxItems: 2
items:
- description: Sierra PHY reset.
- description: Sierra APB reset. This is optional.
reset-names:
minItems: 1
- maxItems: 2
items:
- const: sierra_reset
- const: sierra_apb
reg:
minItems: 1
- maxItems: 2
items:
- description: Offset of the Torrent PHY configuration registers.
- description: Offset of the DPTX PHY configuration registers.
reg-names:
minItems: 1
- maxItems: 2
items:
- const: torrent_phy
- const: dptx_phy
resets:
minItems: 1
- maxItems: 2
items:
- description: Torrent PHY reset.
- description: Torrent APB reset. This is optional.
reset-names:
minItems: 1
- maxItems: 2
items:
- const: torrent_reset
- const: torrent_apb
clock-names:
minItems: 1
- maxItems: 2
items:
- const: ref
- const: xo
clock-names:
minItems: 1
- maxItems: 2
items:
- const: ref
- const: xo
reg:
minItems: 1
- maxItems: 2
items:
- description: Address and length of PHY's common serdes block.
- description: Address and length of PHY's DP_COM control block.
clocks:
minItems: 2
- maxItems: 3
items:
- description: phy config clock
- description: 19.2 MHz ref clk
clock-names:
minItems: 2
- maxItems: 3
items:
- const: cfg_ahb
- const: ref
clock-names:
minItems: 1
- maxItems: 2
items:
- const: fck
- const: usb_x1
resets:
minItems: 1
- maxItems: 2
items:
- description: reset of USB 2.0 host side
- description: reset of USB 2.0 peripheral side
# If you want to use the ssc, the clock-frequency of usb_extal
# must not be 0.
minItems: 2
- maxItems: 3
items:
- const: usb3-if # The funcional clock
- const: usb3s_clk # The usb3's external clock
- description: PAD Pull Control + PAD Schmitt Trigger Enable + PAD Control
- description: PAD Drive Capacity Select
minItems: 1
- maxItems: 4
clocks:
maxItems: 1
clock-names:
minItems: 1
- maxItems: 2
items:
- const: vpu
- const: vapb
clocks:
minItems: 1
- maxItems: 2
items:
- description: Module Clock
- description: Bus Clock
- from local to remote, where ACK from the remote means that communnication
as been stopped on the remote side.
minItems: 1
- maxItems: 4
mbox-names:
items:
- const: shutdown
- const: detach
minItems: 1
- maxItems: 4
memory-region:
description:
list, in the specified order, each representing the corresponding
internal RAM memory region.
minItems: 1
- maxItems: 3
items:
- const: l2ram
- const: l1pram
- description: SRC interrupt
- description: CPU WDOG interrupts out of SRC
minItems: 1
- maxItems: 2
'#reset-cells':
const: 1
interrupts:
minItems: 3
- maxItems: 4
items:
- description: DirError interrupt
- description: DataError interrupt
interrupts:
minItems: 1
- maxItems: 2
items:
- description: RTC Alarm 0
- description: RTC Alarm 1
- description: rtc alarm interrupt
- description: dryice security violation interrupt
minItems: 1
- maxItems: 2
clocks:
maxItems: 1
- description: ipg clock
- description: baud clock
minItems: 1
- maxItems: 2
clock-names:
items:
- const: ipg
- const: baud
minItems: 1
- maxItems: 2
dmas:
items:
clock-names:
description: N = 0 is allowed for SoCs without internal baud clock mux.
minItems: 2
- maxItems: 5
items:
- const: uart
- pattern: '^clk_uart_baud[0-3]$'
interrupts:
minItems: 1
- maxItems: 2
items:
- description: UART core irq
- description: Wakeup irq (RX GPIO)
properties:
reg:
minItems: 2 # On AM437x one of two PRUSS units don't contain Shared RAM.
- maxItems: 3
items:
- description: Address and size of the Data RAM0.
- description: Address and size of the Data RAM1.
reg-names:
minItems: 2
- maxItems: 3
items:
- const: dram0
- const: dram1
minItems: 2
clock-names:
- minItems: 2
items:
- const: pll_a
- const: plla_out0
clocks:
minItems: 1
- maxItems: 2
items:
- description: I2S bit clock
- description:
clock-names:
minItems: 1
- maxItems: 2
items:
- const: i2s
- const: sync_input
- description: Base address and size of SAI common register set.
- description: Base address and size of SAI identification register set.
minItems: 1
- maxItems: 2
ranges:
maxItems: 1
- description: sai_ck clock feeding the internal clock generator.
- description: MCLK clock from a SAI set as master clock provider.
minItems: 1
- maxItems: 2
clock-names:
items:
- const: sai_ck
- const: MCLK
minItems: 1
- maxItems: 2
dmas:
maxItems: 1
clocks:
minItems: 1
- maxItems: 2
items:
- description: controller register bus clock
- description: baud rate generator and delay control clock
reg-names:
minItems: 1
- maxItems: 5
items:
- const: mspi
- const: bspi
interrupt-names:
oneOf:
- minItems: 1
- maxItems: 7
items:
- const: mspi_done
- const: mspi_halted
clocks:
minItems: 1
- maxItems: 2
items:
- description: Bus Clock
- description: Module Clock
clock-names:
minItems: 1
- maxItems: 2
items:
- const: bus
- const: mod
nvmem-cell-names:
minItems: 1
- maxItems: 2
items:
- const: calib
- enum:
interrupts:
minItems: 2
- maxItems: 4
items:
- description: Timer 0 Interrupt
- description: Timer 1 Interrupt
interrupts:
minItems: 1
- maxItems: 5
items:
- description: secure timer irq
- description: non-secure timer irq
interrupts:
minItems: 1
- maxItems: 2
items:
- description: physical timer irq
- description: virtual timer irq
reg:
minItems: 1
- maxItems: 2
items:
- description: 1st view base address
- description: 2nd optional view base address
interrupts:
minItems: 1
- maxItems: 2
items:
- description: Timer 1 interrupt
- description: Timer 2 interrupt
- description: usb irq from max3420
- description: vbus detection irq
minItems: 1
- maxItems: 2
interrupt-names:
items:
- const: udc
- const: vbus
minItems: 1
- maxItems: 2
spi-max-frequency:
maximum: 26000000
reg:
minItems: 2
- maxItems: 3
items:
- description: XUSB device controller registers
- description: XUSB device PCI Config registers
reg-names:
minItems: 2
- maxItems: 3
items:
- const: base
- const: fpci
clocks:
minItems: 4
- maxItems: 5
items:
- description: Clock to enable core XUSB dev clock.
- description: Clock to enable XUSB super speed clock.
clock-names:
minItems: 4
- maxItems: 5
items:
- const: dev
- const: ss
clocks:
minItems: 1
- maxItems: 3
items:
- description: USB 2.0 host
- description: USB 2.0 peripheral
dma-names:
minItems: 2
- maxItems: 4
items:
- const: ch0
- const: ch1
resets:
minItems: 1
- maxItems: 2
items:
- description: USB 2.0 host
- description: USB 2.0 peripheral
- description: Low speed clock
- description: Optional peripheral clock
minItems: 1
- maxItems: 2
clock-names:
items: