+2005-11-14 David Edelsohn <edelsohn@gnu.org>
+
+ * doc/invoke.texi (RS/6000 and PowerPC Options): Add -mmfcrf,
+ -mpopcntb, -mfprnd. Add -mcpu=power5+.
+ * configure.ac: Add test for FP rounding instructions.
+ * configure: Regenerate.
+ * config.in: Regenerate.
+ * config/rs6000/rs6000-c.c (rs6000_cpu_cpp_builtins): Define
+ _ARCH_PPCSQ, _ARCH_PPCGR, _ARCH_PWR4, _ARCH_PWR5, _ARCH_PWR5X if
+ features enabled.
+ * config/rs6000/rs6000.opt (mfprnd): New.
+ * config/rs6000/rs6000.c (processor_target_table): Add power5+.
+ (POWERPC_MASKS): Add MASK_POPCNTB and MASK_FPRND.
+ * config/rs6000/aix52.h (ASM_CPU_SPEC): Add -mpower5+.
+ * config/rs6000/rs6000.h (ASM_CPU_SPEC): Add -mpower5+.
+ (TARGET_FPRND): New.
+ * config/rs6000/rs6000.md (UNSPEC_FRIM, UNSPEC_FRIN, UNSPEC_FRIP,
+ UNSPEC_FRIZ): New.
+ (btrunc<mode>2): New.
+ (ceil<mode>2): New.
+ (floor<mode>2): New.
+ (round<mode>2): New.
+
2005-11-14 Geoffrey Keating <geoffk@apple.com>
* gcc.c (version_compare_spec_function): Use fatal() rather than
#endif
+/* Define if your assembler supports fprnd. */
+#ifndef USED_FOR_TARGET
+#undef HAVE_AS_FPRND
+#endif
+
+
/* Define if your assembler supports the --gdwarf2 option. */
#ifndef USED_FOR_TARGET
#undef HAVE_AS_GDWARF2_DEBUG_FLAG
%{mcpu=power3: -m620} \
%{mcpu=power4: -m620} \
%{mcpu=power5: -m620} \
+%{mcpu=power5+: -m620} \
%{mcpu=powerpc: -mppc} \
%{mcpu=rs64a: -mppc} \
%{mcpu=603: -m603} \
builtin_define ("_ARCH_PWR");
if (TARGET_POWERPC)
builtin_define ("_ARCH_PPC");
+ if (TARGET_PPC_GPOPT)
+ builtin_define ("_ARCH_PPCSQ");
+ if (TARGET_PPC_GFXOPT)
+ builtin_define ("_ARCH_PPCGR");
if (TARGET_POWERPC64)
builtin_define ("_ARCH_PPC64");
+ if (TARGET_MFCRF)
+ builtin_define ("_ARCH_PWR4");
+ if (TARGET_POPCNTB)
+ builtin_define ("_ARCH_PWR5");
+ if (TARGET_FPRND)
+ builtin_define ("_ARCH_PWR5X");
if (! TARGET_POWER && ! TARGET_POWER2 && ! TARGET_POWERPC)
builtin_define ("_ARCH_COM");
if (TARGET_ALTIVEC)
{"power5", PROCESSOR_POWER5,
POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT
| MASK_MFCRF | MASK_POPCNTB},
+ {"power5+", PROCESSOR_POWER5,
+ POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT
+ | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND},
{"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK},
{"powerpc64", PROCESSOR_POWERPC64,
POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT
| MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
- | MASK_MFCRF)
+ | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND)
};
rs6000_init_hard_regno_mode_ok ();
%{mcpu=power3: -mppc64} \
%{mcpu=power4: -mpower4} \
%{mcpu=power5: -mpower4} \
+%{mcpu=power5+: -mpower4} \
%{mcpu=powerpc: -mppc} \
%{mcpu=rios: -mpwr} \
%{mcpu=rios1: -mpwr} \
#define TARGET_POPCNTB 0
#endif
+/* Define TARGET_FPRND if the target assembler does not support the
+ fp rounding instructions. */
+
+#ifndef HAVE_AS_FPRND
+#undef TARGET_FPRND
+#define TARGET_FPRND 0
+#endif
+
#ifndef TARGET_SECURE_PLT
#define TARGET_SECURE_PLT 0
#endif
(UNSPEC_MOVSI_GOT 8)
(UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit
(UNSPEC_FCTIWZ 10)
+ (UNSPEC_FRIM 11)
+ (UNSPEC_FRIN 12)
+ (UNSPEC_FRIP 13)
+ (UNSPEC_FRIZ 14)
(UNSPEC_LD_MPIC 15) ; load_macho_picbase
(UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic
(UNSPEC_TLSGD 17)
"{fcirz|fctiwz} %0,%1"
[(set_attr "type" "fp")])
+(define_insn "btruncdf2"
+ [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
+ (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
+ "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
+ "friz %0,%1"
+ [(set_attr "type" "fp")])
+
+(define_insn "btruncsf2"
+ [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+ (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
+ "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
+ "frizs %0,%1"
+ [(set_attr "type" "fp")])
+
+(define_insn "ceildf2"
+ [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
+ (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
+ "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
+ "frip %0,%1"
+ [(set_attr "type" "fp")])
+
+(define_insn "ceilsf2"
+ [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+ (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
+ "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
+ "frips %0,%1"
+ [(set_attr "type" "fp")])
+
+(define_insn "floordf2"
+ [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
+ (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
+ "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
+ "frim %0,%1"
+ [(set_attr "type" "fp")])
+
+(define_insn "floorsf2"
+ [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+ (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
+ "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
+ "frims %0,%1"
+ [(set_attr "type" "fp")])
+
+(define_insn "rounddf2"
+ [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
+ (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
+ "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
+ "frin %0,%1"
+ [(set_attr "type" "fp")])
+
+(define_insn "roundsf2"
+ [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+ (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
+ "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
+ "frins %0,%1"
+ [(set_attr "type" "fp")])
+
; An UNSPEC is used so we don't have to support SImode in FP registers.
(define_insn "stfiwx"
[(set (match_operand:SI 0 "memory_operand" "=Z")
mmfcrf
Target Report Mask(MFCRF)
-Generate single field mfcr instruction
+Use PowerPC V2.01 single field mfcr instruction
mpopcntb
Target Report Mask(POPCNTB)
-Use PowerPC/AS popcntb instruction
+Use PowerPC V2.02 popcntb instruction
+
+mfprnd
+Target Report Mask(FPRND)
+Use PowerPC V2.02 floating point rounding instructions
maltivec
Target Report Mask(ALTIVEC)
fi
case $target in
+ *-*-aix*) conftest_s=' .machine "pwr5x"
+ .csect .text[PR]
+ frin 1,1';;
+ *) conftest_s=' .machine power5x
+ .text
+ frin 1,1';;
+ esac
+
+ echo "$as_me:$LINENO: checking assembler for fp round support" >&5
+echo $ECHO_N "checking assembler for fp round support... $ECHO_C" >&6
+if test "${gcc_cv_as_powerpc_fprnd+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ gcc_cv_as_powerpc_fprnd=no
+ if test $in_tree_gas = yes; then
+ if test $gcc_cv_gas_vers -ge `expr \( \( 2 \* 1000 \) + 17 \) \* 1000 + 0`
+ then gcc_cv_as_powerpc_fprnd=yes
+fi
+ elif test x$gcc_cv_as != x; then
+ echo "$conftest_s" > conftest.s
+ if { ac_try='$gcc_cv_as -o conftest.o conftest.s >&5'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }
+ then
+ gcc_cv_as_powerpc_fprnd=yes
+ else
+ echo "configure: failed program was" >&5
+ cat conftest.s >&5
+ fi
+ rm -f conftest.o conftest.s
+ fi
+fi
+echo "$as_me:$LINENO: result: $gcc_cv_as_powerpc_fprnd" >&5
+echo "${ECHO_T}$gcc_cv_as_powerpc_fprnd" >&6
+if test $gcc_cv_as_powerpc_fprnd = yes; then
+
+cat >>confdefs.h <<\_ACEOF
+#define HAVE_AS_FPRND 1
+_ACEOF
+
+fi
+
+ case $target in
*-*-aix*) conftest_s=' .csect .text[PR]
LCF..0:
addis 11,30,_GLOBAL_OFFSET_TABLE_-LCF..0@ha';;
[Define if your assembler supports popcntb field.])])
case $target in
+ *-*-aix*) conftest_s=' .machine "pwr5x"
+ .csect .text[[PR]]
+ frin 1,1';;
+ *) conftest_s=' .machine power5x
+ .text
+ frin 1,1';;
+ esac
+
+ gcc_GAS_CHECK_FEATURE([fp round support],
+ gcc_cv_as_powerpc_fprnd, [2,17,0],,
+ [$conftest_s],,
+ [AC_DEFINE(HAVE_AS_FPRND, 1,
+ [Define if your assembler supports fprnd.])])
+
+ case $target in
*-*-aix*) conftest_s=' .csect .text[[PR]]
LCF..0:
addis 11,30,_GLOBAL_OFFSET_TABLE_-LCF..0@ha';;
-maltivec -mno-altivec @gol
-mpowerpc-gpopt -mno-powerpc-gpopt @gol
-mpowerpc-gfxopt -mno-powerpc-gfxopt @gol
+-mmfcrf -mno-mfcrf -mpopcntb -mno-popcntb -mfprnd -mno-fprnd @gol
-mnew-mnemonics -mold-mnemonics @gol
-mfull-toc -mminimal-toc -mno-fp-in-toc -mno-sum-in-toc @gol
-m64 -m32 -mxl-compat -mno-xl-compat -mpe @gol
@itemx -mno-powerpc-gfxopt
@itemx -mpowerpc64
@itemx -mno-powerpc64
+@itemx -mmfcrf
+@itemx -mno-mfcrf
+@itemx -mpopcntb
+@itemx -mno-popcntb
+@itemx -mfprnd
+@itemx -mno-fprnd
@opindex mpower
@opindex mno-power
@opindex mpower2
@opindex mno-powerpc-gfxopt
@opindex mpowerpc64
@opindex mno-powerpc64
+@opindex mmfcrf
+@opindex mno-mfcrf
+@opindex mpopcntb
+@opindex mno-popcntb
+@opindex mfprnd
+@opindex mno-fprnd
GCC supports two related instruction set architectures for the
RS/6000 and PowerPC@. The @dfn{POWER} instruction set are those
instructions supported by the @samp{rios} chip set used in the original
RS/6000 systems and the @dfn{PowerPC} instruction set is the
-architecture of the Motorola MPC5xx, MPC6xx, MPC8xx microprocessors, and
-the IBM 4xx microprocessors.
+architecture of the Freescale MPC5xx, MPC6xx, MPC8xx microprocessors, and
+the IBM 4xx, 6xx, and follow-on microprocessors.
Neither architecture is a subset of the other. However there is a
large common subset of instructions supported by both. An MQ
use the optional PowerPC architecture instructions in the Graphics
group, including floating-point select.
+The @option{-mmfcrf} option allows GCC to generate the move from
+condition register field instruction implemented on the POWER4
+processor and other processors that support the PowerPC V2.01
+architecture.
+The @option{-mpopcntb} option allows GCC to generate the popcount and
+double precision FP reciprocal estimate instruction implemented on the
+POWER5 processor and other processors that support the PowerPC V2.02
+architecture.
+The @option{-mfprnd} option allows GCC to generate the FP round to
+integer instructions implemented on the POWER5+ processor and other
+processors that support the PowerPC V2.03 architecture.
+
The @option{-mpowerpc64} option allows GCC to generate the additional
64-bit instructions that are found in the full PowerPC64 architecture
and to treat GPRs as 64-bit, doubleword quantities. GCC defaults to
@samp{601}, @samp{602}, @samp{603}, @samp{603e}, @samp{604},
@samp{604e}, @samp{620}, @samp{630}, @samp{740}, @samp{7400},
@samp{7450}, @samp{750}, @samp{801}, @samp{821}, @samp{823},
-@samp{860}, @samp{970}, @samp{8540}, @samp{common}, @samp{ec603e}, @samp{G3},
+@samp{860}, @samp{970}, @samp{8540}, @samp{ec603e}, @samp{G3},
@samp{G4}, @samp{G5}, @samp{power}, @samp{power2}, @samp{power3},
-@samp{power4}, @samp{power5}, @samp{powerpc}, @samp{powerpc64},
+@samp{power4}, @samp{power5}, @samp{power5+},
+@samp{common}, @samp{powerpc}, @samp{powerpc64},
@samp{rios}, @samp{rios1}, @samp{rios2}, @samp{rsc}, and @samp{rs64}.
@option{-mcpu=common} selects a completely generic processor. Code
others.
The @option{-mcpu} options automatically enable or disable the
-following options: @option{-maltivec}, @option{-mhard-float},
-@option{-mmfcrf}, @option{-mmultiple}, @option{-mnew-mnemonics},
-@option{-mpower}, @option{-mpower2}, @option{-mpowerpc64},
-@option{-mpowerpc-gpopt}, @option{-mpowerpc-gfxopt},
-@option{-mstring}. The particular options set for any particular CPU
-will vary between compiler versions, depending on what setting seems
-to produce optimal code for that CPU; it doesn't necessarily reflect
-the actual hardware's capabilities. If you wish to set an individual
-option to a particular value, you may specify it after the
-@option{-mcpu} option, like @samp{-mcpu=970 -mno-altivec}.
+following options: @option{-maltivec}, @option{-mfprnd},
+@option{-mhard-float}, @option{-mmfcrf}, @option{-mmultiple},
+@option{-mnew-mnemonics}, @option{-mpopcntb}, @option{-mpower},
+@option{-mpower2}, @option{-mpowerpc64}, @option{-mpowerpc-gpopt},
+@option{-mpowerpc-gfxopt}, @option{-mstring}. The particular options
+set for any particular CPU will vary between compiler versions,
+depending on what setting seems to produce optimal code for that CPU;
+it doesn't necessarily reflect the actual hardware's capabilities. If
+you wish to set an individual option to a particular value, you may
+specify it after the @option{-mcpu} option, like @samp{-mcpu=970
+-mno-altivec}.
On AIX, the @option{-maltivec} and @option{-mpowerpc64} options are
-not enabled or disabled by the @option{-mcpu} option at present, since
+not enabled or disabled by the @option{-mcpu} option at present because
AIX does not have full support for these options. You may still
enable or disable them individually if you're sure it'll work in your
environment.
projects / platform / upstream / gcc.git / commitdiff