arm64: dts: exynos: Add DISP power domain to Exynos 5433 SoC

This patch adds support for DISP power domain to Exynos 5433 SoCs, which
contains following devices: a clock controller, two display controllers
(DECON and DECON TV), their SYSMMUs, MIC, DSI and HDMI video devices.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>

diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 2a03be0..95f30cc 100644 (file)
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -386,6 +386,7 @@
                                <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
                                <&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>,
                                <&cmu_mif CLK_ACLK_DISP_333>;
+                       power-domains = <&pd_disp>;
                };
 
                cmu_aud: clock-controller@114c0000 {
@@ -551,6 +552,13 @@
                        label = "GSCL";
                };
 
+               pd_disp: power-domain@105c4080 {
+                       compatible = "samsung,exynos5433-pd";
+                       reg = <0x105c4080 0x20>;
+                       #power-domain-cells = <0>;
+                       label = "DISP";
+               };
+
                tmu_atlas0: tmu@10060000 {
                        compatible = "samsung,exynos5433-tmu";
                        reg = <0x10060000 0x200>;
@@ -754,6 +762,7 @@
                        clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x",
                                "aclk_xiu_decon0x", "pclk_smmu_decon0x",
                                "sclk_decon_vclk", "sclk_decon_eclk";
+                       power-domains = <&pd_disp>;
                        interrupt-names = "fifo", "vsync", "lcd_sys";
                        interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
@@ -791,6 +800,7 @@
                                      "aclk_xiu_decon0x", "pclk_smmu_decon0x",
                                      "sclk_decon_vclk", "sclk_decon_eclk";
                        samsung,disp-sysreg = <&syscon_disp>;
+                       power-domains = <&pd_disp>;
                        interrupt-names = "fifo", "vsync", "lcd_sys";
                        interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
@@ -816,6 +826,7 @@
                                        "phyclk_mipidphy0_rxclkesc0",
                                        "sclk_rgb_vclk_to_dsim0",
                                        "sclk_mipi";
+                       power-domains = <&pd_disp>;
                        status = "disabled";
                        #address-cells = <1>;
                        #size-cells = <0>;
@@ -839,6 +850,7 @@
                        clocks = <&cmu_disp CLK_PCLK_MIC0>,
                                <&cmu_disp CLK_SCLK_RGB_VCLK_TO_MIC0>;
                        clock-names = "pclk_mic0", "sclk_rgb_vclk_to_mic0";
+                       power-domains = <&pd_disp>;
                        samsung,disp-syscon = <&syscon_disp>;
                        status = "disabled";
 
@@ -980,6 +992,7 @@
                        clock-names = "pclk", "aclk";
                        clocks = <&cmu_disp CLK_PCLK_SMMU_DECON0X>,
                                <&cmu_disp CLK_ACLK_SMMU_DECON0X>;
+                       power-domains = <&pd_disp>;
                        #iommu-cells = <0>;
                };
 
@@ -991,6 +1004,7 @@
                        clocks = <&cmu_disp CLK_PCLK_SMMU_DECON1X>,
                                <&cmu_disp CLK_ACLK_SMMU_DECON1X>;
                        #iommu-cells = <0>;
+                       power-domains = <&pd_disp>;
                };
 
                sysmmu_tv0x: sysmmu@13a20000 {
@@ -1001,6 +1015,7 @@
                        clocks = <&cmu_disp CLK_PCLK_SMMU_TV0X>,
                                <&cmu_disp CLK_ACLK_SMMU_TV0X>;
                        #iommu-cells = <0>;
+                       power-domains = <&pd_disp>;
                };
 
                sysmmu_tv1x: sysmmu@13a30000 {
@@ -1011,6 +1026,7 @@
                        clocks = <&cmu_disp CLK_PCLK_SMMU_TV1X>,
                                <&cmu_disp CLK_ACLK_SMMU_TV1X>;
                        #iommu-cells = <0>;
+                       power-domains = <&pd_disp>;
                };
 
                sysmmu_gscl0: sysmmu@13c80000 {