powerpc/book3s64/hash: Disable 16M linear mapping size if not aligned
authorRussell Currey <ruscur@russell.cc>
Tue, 24 Dec 2019 06:41:25 +0000 (17:41 +1100)
committerMichael Ellerman <mpe@ellerman.id.au>
Thu, 16 Jan 2020 04:59:36 +0000 (14:59 +1000)
With STRICT_KERNEL_RWX on in a relocatable kernel under the hash MMU,
if the position the kernel is loaded at is not 16M aligned things go
horribly wrong. Specifically hash__mark_initmem_nx() will call
hash__change_memory_range() which then aligns down the start address,
and due to the text not being 16M aligned causes some of the kernel
text to be marked non-executable.

We can avoid this when selecting the linear mapping size, so do so and
print a warning. I tested this for various alignments and as long as
the position is 64K aligned it's fine (the base requirement for
powerpc).

Signed-off-by: Russell Currey <ruscur@russell.cc>
[mpe: Add details of the failure mode]
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20191224064126.183670-1-ruscur@russell.cc
arch/powerpc/mm/book3s64/hash_utils.c

index b30435c7d8042a58ec7e4fdd80c29651048c7cb6..523d4d39d11e8c2f9c091cae2b57ec626fb35af7 100644 (file)
@@ -652,6 +652,7 @@ static void init_hpte_page_sizes(void)
 
 static void __init htab_init_page_sizes(void)
 {
+       bool aligned = true;
        init_hpte_page_sizes();
 
        if (!debug_pagealloc_enabled()) {
@@ -659,7 +660,15 @@ static void __init htab_init_page_sizes(void)
                 * Pick a size for the linear mapping. Currently, we only
                 * support 16M, 1M and 4K which is the default
                 */
-               if (mmu_psize_defs[MMU_PAGE_16M].shift)
+               if (IS_ENABLED(STRICT_KERNEL_RWX) &&
+                   (unsigned long)_stext % 0x1000000) {
+                       if (mmu_psize_defs[MMU_PAGE_16M].shift)
+                               pr_warn("Kernel not 16M aligned, "
+                                       "disabling 16M linear map alignment");
+                       aligned = false;
+               }
+
+               if (mmu_psize_defs[MMU_PAGE_16M].shift && aligned)
                        mmu_linear_psize = MMU_PAGE_16M;
                else if (mmu_psize_defs[MMU_PAGE_1M].shift)
                        mmu_linear_psize = MMU_PAGE_1M;