clk: exynos5433: Add CLK_IGNORE_UNUSED flag to clocks occurring hang at sleep

Some clocks are required being unmasked during suspend-to-ram. Otherwise,
PMU will stuck and power line never down.

Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com>

diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
index 1ee33f0..9c15ac4 100644 (file)
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -697,11 +697,14 @@ static struct samsung_gate_clock top_gate_clks[] __initdata = {
        GATE(CLK_SCLK_PCM1_PERIC, "sclk_pcm1_peric", "div_sclk_pcm1",
                        ENABLE_SCLK_TOP_PERIC, 7, CLK_SET_RATE_PARENT, 0),
        GATE(CLK_SCLK_UART2_PERIC, "sclk_uart2_peric", "div_sclk_uart2",
-                       ENABLE_SCLK_TOP_PERIC, 5, CLK_SET_RATE_PARENT, 0),
+                       ENABLE_SCLK_TOP_PERIC, 5, CLK_SET_RATE_PARENT |
+                       CLK_IGNORE_UNUSED, 0),
        GATE(CLK_SCLK_UART1_PERIC, "sclk_uart1_peric", "div_sclk_uart1",
-                       ENABLE_SCLK_TOP_PERIC, 4, CLK_SET_RATE_PARENT, 0),
+                       ENABLE_SCLK_TOP_PERIC, 4, CLK_SET_RATE_PARENT |
+                       CLK_IGNORE_UNUSED, 0),
        GATE(CLK_SCLK_UART0_PERIC, "sclk_uart0_peric", "div_sclk_uart0",
-                       ENABLE_SCLK_TOP_PERIC, 3, CLK_SET_RATE_PARENT, 0),
+                       ENABLE_SCLK_TOP_PERIC, 3, CLK_SET_RATE_PARENT |
+                       CLK_IGNORE_UNUSED, 0),
        GATE(CLK_SCLK_SPI2_PERIC, "sclk_spi2_peric", "div_sclk_spi2_b",
                        ENABLE_SCLK_TOP_PERIC, 2, CLK_SET_RATE_PARENT, 0),
        GATE(CLK_SCLK_SPI1_PERIC, "sclk_spi1_peric", "div_sclk_spi1_b",
@@ -862,7 +865,7 @@ static struct samsung_div_clock cpif_div_clks[] __initdata = {
 static struct samsung_gate_clock cpif_gate_clks[] __initdata = {
        /* ENABLE_SCLK_CPIF */
        GATE(CLK_SCLK_MPHY_PLL, "sclk_mphy_pll", "mout_mphy_pll",
-                       ENABLE_SCLK_CPIF, 9, 0, 0),
+                       ENABLE_SCLK_CPIF, 9, CLK_IGNORE_UNUSED, 0),
        GATE(CLK_SCLK_UFS_MPHY, "sclk_ufs_mphy", "div_sclk_mphy",
                        ENABLE_SCLK_CPIF, 4, 0, 0),
 };
@@ -1718,11 +1721,14 @@ static struct samsung_gate_clock peric_gate_clks[] __initdata = {
        GATE(CLK_SCLK_SPI0, "sclk_spi0", "sclk_spi0_peric", ENABLE_SCLK_PERIC,
                        3, CLK_SET_RATE_PARENT, 0),
        GATE(CLK_SCLK_UART2, "sclk_uart2", "sclk_uart2_peric",
-                       ENABLE_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0),
+                       ENABLE_SCLK_PERIC, 2,
+                       CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
        GATE(CLK_SCLK_UART1, "sclk_uart1", "sclk_uart1_peric",
-                       ENABLE_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0),
+                       ENABLE_SCLK_PERIC, 1,
+                       CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
        GATE(CLK_SCLK_UART0, "sclk_uart0", "sclk_uart0_peric",
-                       ENABLE_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0),
+                       ENABLE_SCLK_PERIC, 0,
+                       CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
 };
 
 static struct samsung_cmu_info peric_cmu_info __initdata = {
@@ -3425,9 +3431,11 @@ static struct samsung_gate_clock gscl_gate_clks[] __initdata = {
        GATE(CLK_ACLK_GSCLNP_111, "aclk_gsclnp_111", "mout_aclk_gscl_111_user",
                        ENABLE_ACLK_GSCL, 6, CLK_IGNORE_UNUSED, 0),
        GATE(CLK_ACLK_GSCLRTND_333, "aclk_gsclrtnd_333",
-                       "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 5, 0, 0),
+                       "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 5,
+                       CLK_IGNORE_UNUSED, 0),
        GATE(CLK_ACLK_GSCLBEND_333, "aclk_gsclbend_333",
-                       "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 4, 0, 0),
+                       "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 4,
+                       CLK_IGNORE_UNUSED, 0),
        GATE(CLK_ACLK_GSD, "aclk_gsd", "mout_aclk_gscl_333_user",
                        ENABLE_ACLK_GSCL, 3, 0, 0),
        GATE(CLK_ACLK_GSCL2, "aclk_gscl2", "mout_aclk_gscl_333_user",