#ifndef __NVKM_PM_H__
#define __NVKM_PM_H__
-#define nvkm_pm(p) container_of((p), struct nvkm_pm, engine)
#include <core/engine.h>
-struct nvkm_perfdom;
-struct nvkm_perfctr;
struct nvkm_pm {
+ const struct nvkm_pm_func *func;
struct nvkm_engine engine;
struct nvkm_object *perfmon;
u32 sequence;
};
-extern struct nvkm_oclass *nv40_pm_oclass;
-extern struct nvkm_oclass *nv50_pm_oclass;
-extern struct nvkm_oclass *g84_pm_oclass;
-extern struct nvkm_oclass *gt200_pm_oclass;
-extern struct nvkm_oclass *gt215_pm_oclass;
-extern struct nvkm_oclass *gf100_pm_oclass;
-extern struct nvkm_oclass *gf108_pm_oclass;
-extern struct nvkm_oclass *gf117_pm_oclass;
-extern struct nvkm_oclass *gk104_pm_oclass;
-extern struct nvkm_oclass gk110_pm_oclass;
+int nv40_pm_new(struct nvkm_device *, int, struct nvkm_pm **);
+int nv50_pm_new(struct nvkm_device *, int, struct nvkm_pm **);
+int g84_pm_new(struct nvkm_device *, int, struct nvkm_pm **);
+int gt200_pm_new(struct nvkm_device *, int, struct nvkm_pm **);
+int gt215_pm_new(struct nvkm_device *, int, struct nvkm_pm **);
+int gf100_pm_new(struct nvkm_device *, int, struct nvkm_pm **);
+int gf108_pm_new(struct nvkm_device *, int, struct nvkm_pm **);
+int gf117_pm_new(struct nvkm_device *, int, struct nvkm_pm **);
+int gk104_pm_new(struct nvkm_device *, int, struct nvkm_pm **);
#endif
.fifo = nv40_fifo_new,
.gr = nv40_gr_new,
// .mpeg = nv40_mpeg_new,
-// .pm = nv40_pm_new,
+ .pm = nv40_pm_new,
// .sw = nv10_sw_new,
};
.fifo = nv40_fifo_new,
.gr = nv40_gr_new,
// .mpeg = nv40_mpeg_new,
-// .pm = nv40_pm_new,
+ .pm = nv40_pm_new,
// .sw = nv10_sw_new,
};
.fifo = nv40_fifo_new,
.gr = nv40_gr_new,
// .mpeg = nv40_mpeg_new,
-// .pm = nv40_pm_new,
+ .pm = nv40_pm_new,
// .sw = nv10_sw_new,
};
.fifo = nv40_fifo_new,
.gr = nv40_gr_new,
// .mpeg = nv40_mpeg_new,
-// .pm = nv40_pm_new,
+ .pm = nv40_pm_new,
// .sw = nv10_sw_new,
};
.fifo = nv40_fifo_new,
.gr = nv44_gr_new,
// .mpeg = nv44_mpeg_new,
-// .pm = nv40_pm_new,
+ .pm = nv40_pm_new,
// .sw = nv10_sw_new,
};
.fifo = nv40_fifo_new,
.gr = nv40_gr_new,
// .mpeg = nv44_mpeg_new,
-// .pm = nv40_pm_new,
+ .pm = nv40_pm_new,
// .sw = nv10_sw_new,
};
.fifo = nv40_fifo_new,
.gr = nv44_gr_new,
// .mpeg = nv44_mpeg_new,
-// .pm = nv40_pm_new,
+ .pm = nv40_pm_new,
// .sw = nv10_sw_new,
};
.fifo = nv40_fifo_new,
.gr = nv40_gr_new,
// .mpeg = nv44_mpeg_new,
-// .pm = nv40_pm_new,
+ .pm = nv40_pm_new,
// .sw = nv10_sw_new,
};
.fifo = nv40_fifo_new,
.gr = nv40_gr_new,
// .mpeg = nv44_mpeg_new,
-// .pm = nv40_pm_new,
+ .pm = nv40_pm_new,
// .sw = nv10_sw_new,
};
.fifo = nv40_fifo_new,
.gr = nv44_gr_new,
// .mpeg = nv44_mpeg_new,
-// .pm = nv40_pm_new,
+ .pm = nv40_pm_new,
// .sw = nv10_sw_new,
};
.fifo = nv40_fifo_new,
.gr = nv40_gr_new,
// .mpeg = nv44_mpeg_new,
-// .pm = nv40_pm_new,
+ .pm = nv40_pm_new,
// .sw = nv10_sw_new,
};
.fifo = nv40_fifo_new,
.gr = nv44_gr_new,
// .mpeg = nv44_mpeg_new,
-// .pm = nv40_pm_new,
+ .pm = nv40_pm_new,
// .sw = nv10_sw_new,
};
.fifo = nv40_fifo_new,
.gr = nv44_gr_new,
// .mpeg = nv44_mpeg_new,
-// .pm = nv40_pm_new,
+ .pm = nv40_pm_new,
// .sw = nv10_sw_new,
};
.fifo = nv50_fifo_new,
.gr = nv50_gr_new,
// .mpeg = nv50_mpeg_new,
-// .pm = nv50_pm_new,
+ .pm = nv50_pm_new,
// .sw = nv50_sw_new,
};
.fifo = nv40_fifo_new,
.gr = nv44_gr_new,
// .mpeg = nv44_mpeg_new,
-// .pm = nv40_pm_new,
+ .pm = nv40_pm_new,
// .sw = nv10_sw_new,
};
.fifo = nv40_fifo_new,
.gr = nv44_gr_new,
// .mpeg = nv44_mpeg_new,
-// .pm = nv40_pm_new,
+ .pm = nv40_pm_new,
// .sw = nv10_sw_new,
};
.fifo = nv40_fifo_new,
.gr = nv44_gr_new,
// .mpeg = nv44_mpeg_new,
-// .pm = nv40_pm_new,
+ .pm = nv40_pm_new,
// .sw = nv10_sw_new,
};
.fifo = g84_fifo_new,
.gr = g84_gr_new,
// .mpeg = g84_mpeg_new,
-// .pm = g84_pm_new,
+ .pm = g84_pm_new,
// .sw = nv50_sw_new,
.vp = g84_vp_new,
};
.fifo = g84_fifo_new,
.gr = g84_gr_new,
// .mpeg = g84_mpeg_new,
-// .pm = g84_pm_new,
+ .pm = g84_pm_new,
// .sw = nv50_sw_new,
.vp = g84_vp_new,
};
.fifo = g84_fifo_new,
.gr = g84_gr_new,
// .mpeg = g84_mpeg_new,
-// .pm = g84_pm_new,
+ .pm = g84_pm_new,
// .sw = nv50_sw_new,
.vp = g84_vp_new,
};
.fifo = g84_fifo_new,
.gr = g84_gr_new,
// .mpeg = g84_mpeg_new,
-// .pm = g84_pm_new,
+ .pm = g84_pm_new,
// .sw = nv50_sw_new,
.vp = g84_vp_new,
};
.cipher = g84_cipher_new,
.bsp = g84_bsp_new,
.disp = g94_disp_new,
-// .pm = g84_pm_new,
+ .pm = g84_pm_new,
};
static const struct nvkm_device_chip
.msvld = g98_msvld_new,
.msppp = g98_msppp_new,
.disp = g94_disp_new,
-// .pm = g84_pm_new,
+ .pm = g84_pm_new,
};
static const struct nvkm_device_chip
.fifo = g84_fifo_new,
.gr = gt200_gr_new,
// .mpeg = g84_mpeg_new,
-// .pm = gt200_pm_new,
+ .pm = gt200_pm_new,
// .sw = nv50_sw_new,
.vp = g84_vp_new,
};
.mspdec = gt215_mspdec_new,
.msppp = gt215_msppp_new,
.msvld = gt215_msvld_new,
-// .pm = gt215_pm_new,
+ .pm = gt215_pm_new,
// .sw = nv50_sw_new,
};
.mspdec = gt215_mspdec_new,
.msppp = gt215_msppp_new,
.msvld = gt215_msvld_new,
-// .pm = gt215_pm_new,
+ .pm = gt215_pm_new,
// .sw = nv50_sw_new,
};
.mspdec = gt215_mspdec_new,
.msppp = gt215_msppp_new,
.msvld = gt215_msvld_new,
-// .pm = gt215_pm_new,
+ .pm = gt215_pm_new,
// .sw = nv50_sw_new,
};
.mspdec = g98_mspdec_new,
.msppp = g98_msppp_new,
.msvld = g98_msvld_new,
-// .pm = g84_pm_new,
+ .pm = g84_pm_new,
.sec = g98_sec_new,
// .sw = nv50_sw_new,
};
.mspdec = g98_mspdec_new,
.msppp = g98_msppp_new,
.msvld = g98_msvld_new,
-// .pm = g84_pm_new,
+ .pm = g84_pm_new,
.sec = g98_sec_new,
// .sw = nv50_sw_new,
};
.mspdec = gt215_mspdec_new,
.msppp = gt215_msppp_new,
.msvld = mcp89_msvld_new,
-// .pm = gt215_pm_new,
+ .pm = gt215_pm_new,
// .sw = nv50_sw_new,
};
.mspdec = gf100_mspdec_new,
.msppp = gf100_msppp_new,
.msvld = gf100_msvld_new,
-// .pm = gf100_pm_new,
+ .pm = gf100_pm_new,
// .sw = gf100_sw_new,
};
.mspdec = gf100_mspdec_new,
.msppp = gf100_msppp_new,
.msvld = gf100_msvld_new,
-// .pm = gf108_pm_new,
+ .pm = gf108_pm_new,
// .sw = gf100_sw_new,
};
.mspdec = gf100_mspdec_new,
.msppp = gf100_msppp_new,
.msvld = gf100_msvld_new,
-// .pm = gf100_pm_new,
+ .pm = gf100_pm_new,
// .sw = gf100_sw_new,
};
.mspdec = gf100_mspdec_new,
.msppp = gf100_msppp_new,
.msvld = gf100_msvld_new,
-// .pm = gf100_pm_new,
+ .pm = gf100_pm_new,
// .sw = gf100_sw_new,
};
.mspdec = gf100_mspdec_new,
.msppp = gf100_msppp_new,
.msvld = gf100_msvld_new,
-// .pm = gf100_pm_new,
+ .pm = gf100_pm_new,
// .sw = gf100_sw_new,
};
.mspdec = gf100_mspdec_new,
.msppp = gf100_msppp_new,
.msvld = gf100_msvld_new,
-// .pm = gf100_pm_new,
+ .pm = gf100_pm_new,
// .sw = gf100_sw_new,
};
.mspdec = gf100_mspdec_new,
.msppp = gf100_msppp_new,
.msvld = gf100_msvld_new,
-// .pm = gf100_pm_new,
+ .pm = gf100_pm_new,
// .sw = gf100_sw_new,
};
.mspdec = gf100_mspdec_new,
.msppp = gf100_msppp_new,
.msvld = gf100_msvld_new,
-// .pm = gf117_pm_new,
+ .pm = gf117_pm_new,
// .sw = gf100_sw_new,
};
.mspdec = gf100_mspdec_new,
.msppp = gf100_msppp_new,
.msvld = gf100_msvld_new,
-// .pm = gf117_pm_new,
+ .pm = gf117_pm_new,
// .sw = gf100_sw_new,
};
.mspdec = gk104_mspdec_new,
.msppp = gf100_msppp_new,
.msvld = gk104_msvld_new,
-// .pm = gk104_pm_new,
+ .pm = gk104_pm_new,
// .sw = gf100_sw_new,
};
.mspdec = gk104_mspdec_new,
.msppp = gf100_msppp_new,
.msvld = gk104_msvld_new,
-// .pm = gk104_pm_new,
+ .pm = gk104_pm_new,
// .sw = gf100_sw_new,
};
.mspdec = gk104_mspdec_new,
.msppp = gf100_msppp_new,
.msvld = gk104_msvld_new,
-// .pm = gk104_pm_new,
+ .pm = gk104_pm_new,
// .sw = gf100_sw_new,
};
.dma = gf119_dma_new,
.fifo = gk20a_fifo_new,
.gr = gk20a_gr_new,
-// .pm = gk104_pm_new,
+ .pm = gk104_pm_new,
// .sw = gf100_sw_new,
};
.mspdec = gk104_mspdec_new,
.msppp = gf100_msppp_new,
.msvld = gk104_msvld_new,
-// .pm = gk110_pm_new,
// .sw = gf100_sw_new,
};
.mspdec = gk104_mspdec_new,
.msppp = gf100_msppp_new,
.msvld = gk104_msvld_new,
-// .pm = gk110_pm_new,
// .sw = gf100_sw_new,
};
switch (device->chipset) {
case 0xc0:
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break;
case 0xc4:
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break;
case 0xc3:
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break;
case 0xce:
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break;
case 0xcf:
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break;
case 0xc1:
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = gf108_pm_oclass;
break;
case 0xc8:
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break;
case 0xd9:
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = gf117_pm_oclass;
break;
case 0xd7:
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = gf117_pm_oclass;
break;
default:
return -EINVAL;
switch (device->chipset) {
case 0xe4:
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass;
break;
case 0xe7:
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass;
break;
case 0xe6:
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass;
break;
case 0xea:
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass;
break;
case 0xf0:
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass;
break;
case 0xf1:
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass;
break;
case 0x106:
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
case 0x40:
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x41:
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x42:
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x43:
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x45:
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x47:
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x49:
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x4b:
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x44:
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x46:
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x4a:
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x4c:
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x4e:
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x63:
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x67:
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x68:
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
default:
return -EINVAL;
case 0x50:
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv50_mpeg_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = nv50_pm_oclass;
break;
case 0x84:
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0x86:
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0x92:
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0x94:
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0x96:
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0x98:
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0xa0:
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = gt200_pm_oclass;
break;
case 0xaa:
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0xac:
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0xa3:
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
break;
case 0xa5:
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
break;
case 0xa8:
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
break;
case 0xaf:
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
- device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
break;
default:
return -EINVAL;
nvkm-y += nvkm/engine/pm/gf108.o
nvkm-y += nvkm/engine/pm/gf117.o
nvkm-y += nvkm/engine/pm/gk104.o
-nvkm-y += nvkm/engine/pm/gk110.o
* Perfdom object classes
******************************************************************************/
static int
-nvkm_perfdom_init(struct nvkm_object *object, void *data, u32 size)
+nvkm_perfdom_init(struct nvkm_perfdom *dom, void *data, u32 size)
{
union {
struct nvif_perfdom_init none;
} *args = data;
- struct nvkm_pm *pm = (void *)object->engine;
- struct nvkm_perfdom *dom = (void *)object;
+ struct nvkm_object *object = &dom->object;
+ struct nvkm_pm *pm = dom->perfmon->pm;
int ret, i;
nvif_ioctl(object, "perfdom init size %d\n", size);
}
static int
-nvkm_perfdom_sample(struct nvkm_object *object, void *data, u32 size)
+nvkm_perfdom_sample(struct nvkm_perfdom *dom, void *data, u32 size)
{
union {
struct nvif_perfdom_sample none;
} *args = data;
- struct nvkm_pm *pm = (void *)object->engine;
- struct nvkm_perfdom *dom;
+ struct nvkm_object *object = &dom->object;
+ struct nvkm_pm *pm = dom->perfmon->pm;
int ret;
nvif_ioctl(object, "perfdom sample size %d\n", size);
}
static int
-nvkm_perfdom_read(struct nvkm_object *object, void *data, u32 size)
+nvkm_perfdom_read(struct nvkm_perfdom *dom, void *data, u32 size)
{
union {
struct nvif_perfdom_read_v0 v0;
} *args = data;
- struct nvkm_pm *pm = (void *)object->engine;
- struct nvkm_perfdom *dom = (void *)object;
+ struct nvkm_object *object = &dom->object;
+ struct nvkm_pm *pm = dom->perfmon->pm;
int ret, i;
nvif_ioctl(object, "perfdom read size %d\n", size);
static int
nvkm_perfdom_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size)
{
+ struct nvkm_perfdom *dom = nvkm_perfdom(object);
switch (mthd) {
case NVIF_PERFDOM_V0_INIT:
- return nvkm_perfdom_init(object, data, size);
+ return nvkm_perfdom_init(dom, data, size);
case NVIF_PERFDOM_V0_SAMPLE:
- return nvkm_perfdom_sample(object, data, size);
+ return nvkm_perfdom_sample(dom, data, size);
case NVIF_PERFDOM_V0_READ:
- return nvkm_perfdom_read(object, data, size);
+ return nvkm_perfdom_read(dom, data, size);
default:
break;
}
}
static void *
-nvkm_perfdom_dtor(struct nvkm_object *base)
+nvkm_perfdom_dtor(struct nvkm_object *object)
{
- struct nvkm_perfdom *dom = nvkm_perfdom(base);
+ struct nvkm_perfdom *dom = nvkm_perfdom(object);
struct nvkm_pm *pm = dom->perfmon->pm;
int i;
}
static int
-nvkm_perfmon_child_get(struct nvkm_object *base, int index,
+nvkm_perfmon_child_get(struct nvkm_object *object, int index,
struct nvkm_oclass *oclass)
{
if (index == 0) {
}
static void *
-nvkm_perfmon_dtor(struct nvkm_object *base)
+nvkm_perfmon_dtor(struct nvkm_object *object)
{
- struct nvkm_perfmon *perfmon = nvkm_perfmon(base);
+ struct nvkm_perfmon *perfmon = nvkm_perfmon(object);
struct nvkm_pm *pm = perfmon->pm;
mutex_lock(&pm->engine.subdev.mutex);
if (pm->perfmon == &perfmon->object)
return 0;
}
-int
-_nvkm_pm_fini(struct nvkm_object *object, bool suspend)
-{
- struct nvkm_pm *pm = (void *)object;
- return nvkm_engine_fini_old(&pm->engine, suspend);
-}
-
-int
-_nvkm_pm_init(struct nvkm_object *object)
+static int
+nvkm_pm_fini(struct nvkm_engine *engine, bool suspend)
{
- struct nvkm_pm *pm = (void *)object;
- return nvkm_engine_init_old(&pm->engine);
+ struct nvkm_pm *pm = nvkm_pm(engine);
+ if (pm->func->fini)
+ pm->func->fini(pm);
+ return 0;
}
-void
-_nvkm_pm_dtor(struct nvkm_object *object)
+static void *
+nvkm_pm_dtor(struct nvkm_engine *engine)
{
- struct nvkm_pm *pm = (void *)object;
+ struct nvkm_pm *pm = nvkm_pm(engine);
struct nvkm_perfdom *dom, *next_dom;
struct nvkm_perfsrc *src, *next_src;
kfree(src);
}
- nvkm_engine_destroy(&pm->engine);
+ return pm;
}
static const struct nvkm_engine_func
nvkm_pm = {
+ .dtor = nvkm_pm_dtor,
+ .fini = nvkm_pm_fini,
.base.sclass = nvkm_pm_oclass_get,
};
int
-nvkm_pm_create_(struct nvkm_object *parent, struct nvkm_object *engine,
- struct nvkm_oclass *oclass, int length, void **pobject)
+nvkm_pm_ctor(const struct nvkm_pm_func *func, struct nvkm_device *device,
+ int index, struct nvkm_pm *pm)
{
- struct nvkm_pm *pm;
- int ret;
-
- ret = nvkm_engine_create_(parent, engine, oclass, true, "PPM",
- "pm", length, pobject);
- pm = *pobject;
- if (ret)
- return ret;
-
- pm->engine.func = &nvkm_pm;
-
+ pm->func = func;
INIT_LIST_HEAD(&pm->domains);
INIT_LIST_HEAD(&pm->sources);
- return 0;
+ return nvkm_engine_ctor(&nvkm_pm, device, index, 0, true, &pm->engine);
}
{}
};
-struct nvkm_oclass *
-g84_pm_oclass = &(struct nv40_pm_oclass) {
- .base.handle = NV_ENGINE(PM, 0x84),
- .base.ofuncs = &(struct nvkm_ofuncs) {
- .ctor = nv40_pm_ctor,
- .dtor = _nvkm_pm_dtor,
- .init = _nvkm_pm_init,
- .fini = _nvkm_pm_fini,
- },
- .doms = g84_pm,
-}.base;
+int
+g84_pm_new(struct nvkm_device *device, int index, struct nvkm_pm **ppm)
+{
+ return nv40_pm_new_(g84_pm, device, index, ppm);
+}
struct nvkm_perfctr *ctr)
{
struct nvkm_device *device = pm->engine.subdev.device;
- struct gf100_pm_cntr *cntr = (void *)ctr;
u32 log = ctr->logic_op;
u32 src = 0x00000000;
int i;
nvkm_wr32(device, dom->addr + 0x09c, 0x00040002 | (dom->mode << 3));
nvkm_wr32(device, dom->addr + 0x100, 0x00000000);
- nvkm_wr32(device, dom->addr + 0x040 + (cntr->base.slot * 0x08), src);
- nvkm_wr32(device, dom->addr + 0x044 + (cntr->base.slot * 0x08), log);
+ nvkm_wr32(device, dom->addr + 0x040 + (ctr->slot * 0x08), src);
+ nvkm_wr32(device, dom->addr + 0x044 + (ctr->slot * 0x08), log);
}
static void
struct nvkm_perfctr *ctr)
{
struct nvkm_device *device = pm->engine.subdev.device;
- struct gf100_pm_cntr *cntr = (void *)ctr;
- switch (cntr->base.slot) {
- case 0: cntr->base.ctr = nvkm_rd32(device, dom->addr + 0x08c); break;
- case 1: cntr->base.ctr = nvkm_rd32(device, dom->addr + 0x088); break;
- case 2: cntr->base.ctr = nvkm_rd32(device, dom->addr + 0x080); break;
- case 3: cntr->base.ctr = nvkm_rd32(device, dom->addr + 0x090); break;
+ switch (ctr->slot) {
+ case 0: ctr->ctr = nvkm_rd32(device, dom->addr + 0x08c); break;
+ case 1: ctr->ctr = nvkm_rd32(device, dom->addr + 0x088); break;
+ case 2: ctr->ctr = nvkm_rd32(device, dom->addr + 0x080); break;
+ case 3: ctr->ctr = nvkm_rd32(device, dom->addr + 0x090); break;
}
dom->clk = nvkm_rd32(device, dom->addr + 0x070);
}
.next = gf100_perfctr_next,
};
-int
-gf100_pm_fini(struct nvkm_object *object, bool suspend)
+static void
+gf100_pm_fini(struct nvkm_pm *pm)
{
- struct nvkm_pm *pm = (void *)object;
struct nvkm_device *device = pm->engine.subdev.device;
nvkm_mask(device, 0x000200, 0x10000000, 0x00000000);
nvkm_mask(device, 0x000200, 0x10000000, 0x10000000);
- return nvkm_pm_fini(pm, suspend);
}
+static const struct nvkm_pm_func
+gf100_pm_ = {
+ .fini = gf100_pm_fini,
+};
+
int
-gf100_pm_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
- struct nvkm_oclass *oclass, void *data, u32 size,
- struct nvkm_object **pobject)
+gf100_pm_new_(const struct gf100_pm_func *func, struct nvkm_device *device,
+ int index, struct nvkm_pm **ppm)
{
- struct gf100_pm_oclass *mclass = (void *)oclass;
- struct nvkm_device *device = (void *)parent;
struct nvkm_pm *pm;
u32 mask;
int ret;
- ret = nvkm_pm_create(parent, engine, oclass, &pm);
- *pobject = nv_object(pm);
+ if (!(pm = *ppm = kzalloc(sizeof(*pm), GFP_KERNEL)))
+ return -ENOMEM;
+
+ ret = nvkm_pm_ctor(&gf100_pm_, device, index, pm);
if (ret)
return ret;
/* HUB */
ret = nvkm_perfdom_new(pm, "hub", 0, 0x1b0000, 0, 0x200,
- mclass->doms_hub);
+ func->doms_hub);
if (ret)
return ret;
mask &= ~nvkm_rd32(device, 0x022584);
ret = nvkm_perfdom_new(pm, "gpc", mask, 0x180000,
- 0x1000, 0x200, mclass->doms_gpc);
+ 0x1000, 0x200, func->doms_gpc);
if (ret)
return ret;
mask &= ~nvkm_rd32(device, 0x0225c8);
ret = nvkm_perfdom_new(pm, "part", mask, 0x1a0000,
- 0x1000, 0x200, mclass->doms_part);
+ 0x1000, 0x200, func->doms_part);
if (ret)
return ret;
return 0;
}
-struct nvkm_oclass *
-gf100_pm_oclass = &(struct gf100_pm_oclass) {
- .base.handle = NV_ENGINE(PM, 0xc0),
- .base.ofuncs = &(struct nvkm_ofuncs) {
- .ctor = gf100_pm_ctor,
- .dtor = _nvkm_pm_dtor,
- .init = _nvkm_pm_init,
- .fini = gf100_pm_fini,
- },
- .doms_gpc = gf100_pm_gpc,
- .doms_hub = gf100_pm_hub,
+static const struct gf100_pm_func
+gf100_pm = {
+ .doms_gpc = gf100_pm_gpc,
+ .doms_hub = gf100_pm_hub,
.doms_part = gf100_pm_part,
-}.base;
+};
+
+int
+gf100_pm_new(struct nvkm_device *device, int index, struct nvkm_pm **ppm)
+{
+ return gf100_pm_new_(&gf100_pm, device, index, ppm);
+}
#define __NVKM_PM_NVC0_H__
#include "priv.h"
-struct gf100_pm_oclass {
- struct nvkm_oclass base;
+struct gf100_pm_func {
const struct nvkm_specdom *doms_hub;
const struct nvkm_specdom *doms_gpc;
const struct nvkm_specdom *doms_part;
};
-int gf100_pm_ctor(struct nvkm_object *, struct nvkm_object *,
- struct nvkm_oclass *, void *data, u32 size,
- struct nvkm_object **pobject);
-
-struct gf100_pm_cntr {
- struct nvkm_perfctr base;
-};
+int gf100_pm_new_(const struct gf100_pm_func *, struct nvkm_device *,
+ int index, struct nvkm_pm **);
extern const struct nvkm_funcdom gf100_perfctr_func;
-int gf100_pm_fini(struct nvkm_object *, bool);
-
extern const struct nvkm_specdom gf100_pm_gpc[];
extern const struct nvkm_specsrc gf100_pbfb_sources[];
extern const struct nvkm_specsrc gf100_pmfb_sources[];
-
#endif
{}
};
-struct nvkm_oclass *
-gf108_pm_oclass = &(struct gf100_pm_oclass) {
- .base.handle = NV_ENGINE(PM, 0xc1),
- .base.ofuncs = &(struct nvkm_ofuncs) {
- .ctor = gf100_pm_ctor,
- .dtor = _nvkm_pm_dtor,
- .init = _nvkm_pm_init,
- .fini = gf100_pm_fini,
- },
- .doms_hub = gf108_pm_hub,
- .doms_gpc = gf100_pm_gpc,
+static const struct gf100_pm_func
+gf108_pm = {
+ .doms_gpc = gf100_pm_gpc,
+ .doms_hub = gf108_pm_hub,
.doms_part = gf108_pm_part,
-}.base;
+};
+
+int
+gf108_pm_new(struct nvkm_device *device, int index, struct nvkm_pm **ppm)
+{
+ return gf100_pm_new_(&gf108_pm, device, index, ppm);
+}
{}
};
-struct nvkm_oclass *
-gf117_pm_oclass = &(struct gf100_pm_oclass) {
- .base.handle = NV_ENGINE(PM, 0xd7),
- .base.ofuncs = &(struct nvkm_ofuncs) {
- .ctor = gf100_pm_ctor,
- .dtor = _nvkm_pm_dtor,
- .init = _nvkm_pm_init,
- .fini = gf100_pm_fini,
- },
- .doms_gpc = gf100_pm_gpc,
- .doms_hub = gf117_pm_hub,
+static const struct gf100_pm_func
+gf117_pm = {
+ .doms_gpc = gf100_pm_gpc,
+ .doms_hub = gf117_pm_hub,
.doms_part = gf117_pm_part,
-}.base;
+};
+
+int
+gf117_pm_new(struct nvkm_device *device, int index, struct nvkm_pm **ppm)
+{
+ return gf100_pm_new_(&gf117_pm, device, index, ppm);
+}
{}
};
-struct nvkm_oclass *
-gk104_pm_oclass = &(struct gf100_pm_oclass) {
- .base.handle = NV_ENGINE(PM, 0xe0),
- .base.ofuncs = &(struct nvkm_ofuncs) {
- .ctor = gf100_pm_ctor,
- .dtor = _nvkm_pm_dtor,
- .init = _nvkm_pm_init,
- .fini = gf100_pm_fini,
- },
- .doms_gpc = gk104_pm_gpc,
- .doms_hub = gk104_pm_hub,
+static const struct gf100_pm_func
+gk104_pm = {
+ .doms_gpc = gk104_pm_gpc,
+ .doms_hub = gk104_pm_hub,
.doms_part = gk104_pm_part,
-}.base;
+};
+
+int
+gk104_pm_new(struct nvkm_device *device, int index, struct nvkm_pm **ppm)
+{
+ return gf100_pm_new_(&gk104_pm, device, index, ppm);
+}
+++ /dev/null
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-#include "gf100.h"
-
-static int
-gk110_pm_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
- struct nvkm_oclass *oclass, void *data, u32 size,
- struct nvkm_object **pobject)
-{
- struct nvkm_pm *pm;
- int ret;
-
- ret = nvkm_pm_create(parent, engine, oclass, &pm);
- *pobject = nv_object(pm);
- if (ret)
- return ret;
-
- return 0;
-}
-
-struct nvkm_oclass
-gk110_pm_oclass = {
- .handle = NV_ENGINE(PM, 0xf0),
- .ofuncs = &(struct nvkm_ofuncs) {
- .ctor = gk110_pm_ctor,
- .dtor = _nvkm_pm_dtor,
- .init = _nvkm_pm_init,
- .fini = gf100_pm_fini,
- },
-};
{}
};
-struct nvkm_oclass *
-gt200_pm_oclass = &(struct nv40_pm_oclass) {
- .base.handle = NV_ENGINE(PM, 0xa0),
- .base.ofuncs = &(struct nvkm_ofuncs) {
- .ctor = nv40_pm_ctor,
- .dtor = _nvkm_pm_dtor,
- .init = _nvkm_pm_init,
- .fini = _nvkm_pm_fini,
- },
- .doms = gt200_pm,
-}.base;
+int
+gt200_pm_new(struct nvkm_device *device, int index, struct nvkm_pm **ppm)
+{
+ return nv40_pm_new_(gt200_pm, device, index, ppm);
+}
{}
};
-struct nvkm_oclass *
-gt215_pm_oclass = &(struct nv40_pm_oclass) {
- .base.handle = NV_ENGINE(PM, 0xa3),
- .base.ofuncs = &(struct nvkm_ofuncs) {
- .ctor = nv40_pm_ctor,
- .dtor = _nvkm_pm_dtor,
- .init = _nvkm_pm_init,
- .fini = _nvkm_pm_fini,
- },
- .doms = gt215_pm,
-}.base;
+int
+gt215_pm_new(struct nvkm_device *device, int index, struct nvkm_pm **ppm)
+{
+ return nv40_pm_new_(gt215_pm, device, index, ppm);
+}
struct nvkm_perfctr *ctr)
{
struct nvkm_device *device = pm->engine.subdev.device;
- struct nv40_pm_cntr *cntr = (void *)ctr;
u32 log = ctr->logic_op;
u32 src = 0x00000000;
int i;
src |= ctr->signal[i] << (i * 8);
nvkm_wr32(device, 0x00a7c0 + dom->addr, 0x00000001 | (dom->mode << 4));
- nvkm_wr32(device, 0x00a400 + dom->addr + (cntr->base.slot * 0x40), src);
- nvkm_wr32(device, 0x00a420 + dom->addr + (cntr->base.slot * 0x40), log);
+ nvkm_wr32(device, 0x00a400 + dom->addr + (ctr->slot * 0x40), src);
+ nvkm_wr32(device, 0x00a420 + dom->addr + (ctr->slot * 0x40), log);
}
static void
struct nvkm_perfctr *ctr)
{
struct nvkm_device *device = pm->engine.subdev.device;
- struct nv40_pm_cntr *cntr = (void *)ctr;
- switch (cntr->base.slot) {
- case 0: cntr->base.ctr = nvkm_rd32(device, 0x00a700 + dom->addr); break;
- case 1: cntr->base.ctr = nvkm_rd32(device, 0x00a6c0 + dom->addr); break;
- case 2: cntr->base.ctr = nvkm_rd32(device, 0x00a680 + dom->addr); break;
- case 3: cntr->base.ctr = nvkm_rd32(device, 0x00a740 + dom->addr); break;
+ switch (ctr->slot) {
+ case 0: ctr->ctr = nvkm_rd32(device, 0x00a700 + dom->addr); break;
+ case 1: ctr->ctr = nvkm_rd32(device, 0x00a6c0 + dom->addr); break;
+ case 2: ctr->ctr = nvkm_rd32(device, 0x00a680 + dom->addr); break;
+ case 3: ctr->ctr = nvkm_rd32(device, 0x00a740 + dom->addr); break;
}
dom->clk = nvkm_rd32(device, 0x00a600 + dom->addr);
}
.next = nv40_perfctr_next,
};
+static const struct nvkm_pm_func
+nv40_pm_ = {
+};
+
+int
+nv40_pm_new_(const struct nvkm_specdom *doms, struct nvkm_device *device,
+ int index, struct nvkm_pm **ppm)
+{
+ struct nv40_pm *pm;
+ int ret;
+
+ if (!(pm = kzalloc(sizeof(*pm), GFP_KERNEL)))
+ return -ENOMEM;
+ *ppm = &pm->base;
+
+ ret = nvkm_pm_ctor(&nv40_pm_, device, index, &pm->base);
+ if (ret)
+ return ret;
+
+ return nvkm_perfdom_new(&pm->base, "pc", 0, 0, 0, 4, doms);
+}
+
static const struct nvkm_specdom
nv40_pm[] = {
{ 0x20, (const struct nvkm_specsig[]) {
};
int
-nv40_pm_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
- struct nvkm_oclass *oclass, void *data, u32 size,
- struct nvkm_object **pobject)
+nv40_pm_new(struct nvkm_device *device, int index, struct nvkm_pm **ppm)
{
- struct nv40_pm_oclass *mclass = (void *)oclass;
- struct nv40_pm *pm;
- int ret;
-
- ret = nvkm_pm_create(parent, engine, oclass, &pm);
- *pobject = nv_object(pm);
- if (ret)
- return ret;
-
- ret = nvkm_perfdom_new(&pm->base, "pc", 0, 0, 0, 4, mclass->doms);
- if (ret)
- return ret;
-
- return 0;
+ return nv40_pm_new_(nv40_pm, device, index, ppm);
}
-
-struct nvkm_oclass *
-nv40_pm_oclass = &(struct nv40_pm_oclass) {
- .base.handle = NV_ENGINE(PM, 0x40),
- .base.ofuncs = &(struct nvkm_ofuncs) {
- .ctor = nv40_pm_ctor,
- .dtor = _nvkm_pm_dtor,
- .init = _nvkm_pm_init,
- .fini = _nvkm_pm_fini,
- },
- .doms = nv40_pm,
-}.base;
#ifndef __NVKM_PM_NV40_H__
#define __NVKM_PM_NV40_H__
+#define nv40_pm(p) container_of((p), struct nv40_pm, base)
#include "priv.h"
-struct nv40_pm_oclass {
- struct nvkm_oclass base;
- const struct nvkm_specdom *doms;
-};
-
struct nv40_pm {
struct nvkm_pm base;
u32 sequence;
};
-int nv40_pm_ctor(struct nvkm_object *, struct nvkm_object *,
- struct nvkm_oclass *, void *data, u32 size,
- struct nvkm_object **pobject);
-
-struct nv40_pm_cntr {
- struct nvkm_perfctr base;
-};
-
+int nv40_pm_new_(const struct nvkm_specdom *, struct nvkm_device *,
+ int index, struct nvkm_pm **);
extern const struct nvkm_funcdom nv40_perfctr_func;
#endif
{}
};
-struct nvkm_oclass *
-nv50_pm_oclass = &(struct nv40_pm_oclass) {
- .base.handle = NV_ENGINE(PM, 0x50),
- .base.ofuncs = &(struct nvkm_ofuncs) {
- .ctor = nv40_pm_ctor,
- .dtor = _nvkm_pm_dtor,
- .init = _nvkm_pm_init,
- .fini = _nvkm_pm_fini,
- },
- .doms = nv50_pm,
-}.base;
+int
+nv50_pm_new(struct nvkm_device *device, int index, struct nvkm_pm **ppm)
+{
+ return nv40_pm_new_(nv50_pm, device, index, ppm);
+}
#ifndef __NVKM_PM_PRIV_H__
#define __NVKM_PM_PRIV_H__
+#define nvkm_pm(p) container_of((p), struct nvkm_pm, engine)
#include <engine/pm.h>
+int nvkm_pm_ctor(const struct nvkm_pm_func *, struct nvkm_device *,
+ int index, struct nvkm_pm *);
+
+struct nvkm_pm_func {
+ void (*fini)(struct nvkm_pm *);
+};
+
struct nvkm_perfctr {
struct list_head head;
u8 domain;
struct nvkm_object object;
struct nvkm_pm *pm;
};
-
-#define nvkm_pm_create(p,e,o,d) \
- nvkm_pm_create_((p), (e), (o), sizeof(**d), (void **)d)
-#define nvkm_pm_dtor(p) ({ \
- struct nvkm_pm *c = (p); \
- _nvkm_pm_dtor(nv_object(c)); \
-})
-#define nvkm_pm_init(p) ({ \
- struct nvkm_pm *c = (p); \
- _nvkm_pm_init(nv_object(c)); \
-})
-#define nvkm_pm_fini(p,s) ({ \
- struct nvkm_pm *c = (p); \
- _nvkm_pm_fini(nv_object(c), (s)); \
-})
-
-int nvkm_pm_create_(struct nvkm_object *, struct nvkm_object *,
- struct nvkm_oclass *, int, void **);
-void _nvkm_pm_dtor(struct nvkm_object *);
-int _nvkm_pm_init(struct nvkm_object *);
-int _nvkm_pm_fini(struct nvkm_object *, bool);
#endif
projects / platform / kernel / linux-exynos.git / commitdiff