clk: update for pcie range setting

PD#146333: update for pcie range setting

Change-Id: Ic105ec91bd480ab0d4b980eda90ccbcd1d7baa2c
Signed-off-by: Yun Cai <yun.cai@amlogic.com>

diff --git a/drivers/amlogic/clk/axg/axg_clk-pll.c b/drivers/amlogic/clk/axg/axg_clk-pll.c
index e5f4663..2a1c669 100644 (file)
--- a/drivers/amlogic/clk/axg/axg_clk-pll.c
+++ b/drivers/amlogic/clk/axg/axg_clk-pll.c
@@ -59,13 +59,13 @@
 /* AXG */
 #define AXG_MIPI_CNTL0_ENABLE   BIT(29)
 #define AXG_MIPI_CNTL0_BANDGAP  BIT(26)
-#define AXG_PCIE_PLL_CNTL 0x40010242
-#define AXG_PCIE_PLL_CNTL1 0xc084b2ab
+#define AXG_PCIE_PLL_CNTL 0x400106c8
+#define AXG_PCIE_PLL_CNTL1 0x0084a2aa
 #define AXG_PCIE_PLL_CNTL2 0xb75020be
-#define AXG_PCIE_PLL_CNTL3 0x0a5aaa88
+#define AXG_PCIE_PLL_CNTL3 0x0a47488e
 #define AXG_PCIE_PLL_CNTL4 0xc000004d
 #define AXG_PCIE_PLL_CNTL5 0x00078000
-#define AXG_PCIE_PLL_CNTL6 0x003303de
+#define AXG_PCIE_PLL_CNTL6 0x002323de
 
 #define AXG_HIFI_PLL_CNTL1 0xc084b000
 #define AXG_HIFI_PLL_CNTL2 0xb75020be