intel/isl: Properly set SeparateStencilBufferEnable on gen5-6

On gen5-6, SeparateStencilBufferEnable and HierarchicalDepthBufferEnable
come hand in hand and we have to set either both or neither.

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>

diff --git a/src/intel/isl/isl_emit_depth_stencil.c b/src/intel/isl/isl_emit_depth_stencil.c
index 339da28..0d541fd 100644 (file)
--- a/src/intel/isl/isl_emit_depth_stencil.c
+++ b/src/intel/isl/isl_emit_depth_stencil.c
@@ -113,6 +113,16 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch,
 #endif
    }
 
+#if GEN_GEN == 5 || GEN_GEN == 6
+   const bool separate_stencil =
+      info->stencil_surf && info->stencil_surf->format == ISL_FORMAT_R8_UINT;
+   if (separate_stencil || info->hiz_usage == ISL_AUX_USAGE_HIZ) {
+      assert(ISL_DEV_USE_SEPARATE_STENCIL(dev));
+      db.SeparateStencilBufferEnable = true;
+      db.HierarchicalDepthBufferEnable = true;
+   }
+#endif
+
 #if GEN_GEN >= 6
    struct GENX(3DSTATE_STENCIL_BUFFER) sb = {
       GENX(3DSTATE_STENCIL_BUFFER_header),
@@ -151,9 +161,6 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch,
           info->hiz_usage == ISL_AUX_USAGE_HIZ);
    if (info->hiz_usage == ISL_AUX_USAGE_HIZ) {
       db.HierarchicalDepthBufferEnable = true;
-#if GEN_GEN == 5 || GEN_GEN == 6
-      db.SeparateStencilBufferEnable = true;
-#endif
 
       hiz.SurfaceBaseAddress = info->hiz_address;
       hiz.HierarchicalDepthBufferMOCS = info->mocs;