Readme entry
configure --[enable/disable]-cpu-sse3
processor capability test
Patch by: Jim Kukunas <james.t.kukunas@linux.intel.com>
git-svn-id: http://svn.enlightenment.org/svn/e/trunk/evas@63697
7cbeb6ba-43b4-40fd-8cce-
4c39aea84d33
fallback routines as i haven't managed to come up with any arm assembly that
actually can beat the c code (when compiled with all optimizations) in speed.
+--enable-cpu-sse3
+
+this enables sse3 optimizations available in the Intel Pentium4, Core, Xeon,
+and Atom processors, as well as the AMD Athlon64, Phenom, Opteron, and Turion
+processors.
+
--enable-cpu-neon
)
#######################################
+## SSE3
+build_cpu_sse3="no"
+case $host_cpu in
+ i*86)
+ build_cpu_sse3="yes"
+ ;;
+ x86_64)
+ build_cpu_sse3="yes"
+ ;;
+ amd64)
+ build_cpu_sse3="yes"
+ ;;
+esac
+AC_MSG_CHECKING(whether to build sse3 code)
+AC_ARG_ENABLE(cpu-sse3,
+ AS_HELP_STRING([--enable-cpu-sse3],[enable sse3 code]),
+ [
+ if test "x$enableval" = "xyes" ; then
+ AC_MSG_RESULT(yes)
+ AC_DEFINE(BUILD_SSE3, 1, [Build SSE3 Code])
+ build_cpu_sse3="yes"
+ else
+ AC_MSG_RESULT(no)
+ build_cpu_sse3="no"
+ fi
+ ],
+ [
+ AC_MSG_RESULT($build_cpu_sse3)
+ if test "x$build_cpu_sse3" = "xyes" ; then
+ AC_DEFINE(BUILD_SSE3, 1, [Build SSE3 Code])
+ fi
+ ]
+)
+
+
+EVAS_SSE3_CFLAGS="-msse3 "
+if test "x$build_cpu_sse3" = "xyes" ; then
+ CFLAGS="${CFLAGS} ${EVAS_SSE3_CFLAGS}"
+fi
+
+AC_SUBST(CFLAGS)
+
+#######################################
## ALTIVEC
build_cpu_altivec="no"
case $host_cpu in
echo " Fallback C Code.........: $build_cpu_c"
echo " MMX.....................: $build_cpu_mmx"
echo " SSE.....................: $build_cpu_sse"
+echo " SSE3....................: $build_cpu_sse3"
echo " ALTIVEC.................: $build_cpu_altivec"
echo " NEON....................: $build_cpu_neon"
echo " Thread Support..........: $build_pthreads"
#include "evas_mmx.h"
#endif
+#if defined BUILD_SSE3
+#include <immintrin.h>
+#endif
+
#if defined (HAVE_STRUCT_SIGACTION) && defined (HAVE_SIGLONGJMP)
#include <signal.h>
#include <setjmp.h>
}
void
+evas_common_cpu_sse3_test(void)
+{
+#ifdef BUILD_SSE3
+ int data[4];
+
+ __m128i val = _mm_lddqu_si128((__m128i *)data);
+#endif
+}
+
+void
evas_common_cpu_altivec_test(void)
{
#ifdef __POWERPC__
evas_common_cpu_end_opt();
if (getenv("EVAS_CPU_NO_SSE"))
cpu_feature_mask &= ~CPU_FEATURE_SSE;
+#ifdef BUILD_SSE3
+ cpu_feature_mask |= CPU_FEATURE_SSE3 *
+ evas_common_cpu_feature_test(evas_common_cpu_sse3_test);
+ evas_common_cpu_end_opt();
+ if(getenv("EVAS_CPU_NO_SSE3"))
+ cpu_feature_mask &= ~CPU_FEATURE_SSE3;
+#endif /* BUILD_SSE3 */
#endif /* BUILD_SSE */
#endif /* BUILD_MMX */
#ifdef __POWERPC__
#define CPU_SSE2 4
/* cpu flags count */
#define CPU_NEON 5
+/* CPU SSE3 */
+#define CPU_SSE3 6
/* cpu flags count */
-#define CPU_LAST 6
+#define CPU_LAST 7
/* some useful constants */
CPU_FEATURE_ALTIVEC = (1 << 3),
CPU_FEATURE_VIS = (1 << 4),
CPU_FEATURE_VIS2 = (1 << 5),
- CPU_FEATURE_NEON = (1 << 6)
+ CPU_FEATURE_NEON = (1 << 6),
+ CPU_FEATURE_SSE3 = (1 << 7)
} CPU_Features;
typedef enum _Font_Hint_Flags
/*#define BUILD_MMX*/
/*#define BUILD_SSE*/
+/*#define BUILD_SSE3*/
/*#define BUILD_C*/
/*#define BUILD_LOADER_PNG*/
/* check in that the user configured it right */
#ifndef BUILD_MMX
-# ifndef BUILD_SSE
-# ifndef BUILD_C
+# ifndef BUILD_SSE3
+# ifndef BUILD_SSE
+# ifndef BUILD_C
# error "Please Read the README"
+ #endif
# endif
# endif
#endif