arm: Split xorsi with constant after reload.

This puts xorsi3 in the same format as andsi3 and iorsi3.
This similarity fixes code generation issues with splitting
atomic_fetch_xor post-reload.

        * config/arm/arm.md (*arm_xorsi3): Match iorsi3 and perform
        post-reload splitting.

From-SVN: r182562

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index f5ec754..4304d6e 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,8 @@
 2011-12-20  Richard Henderson  <rth@redhat.com>
 
+       * config/arm/arm.md (*arm_xorsi3): Match iorsi3 and perform
+       post-reload splitting.
+
        * config/arm/arm.md (*arm_cmpdi_unsigned): Enable for thumb2.
        * config/arm/arm.c (arm_select_cc_mode): Use it.
 

diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index a5b1df6..751997f 100644 (file)
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -3061,13 +3061,25 @@
     }"
 )
 
-(define_insn "*arm_xorsi3"
-  [(set (match_operand:SI         0 "s_register_operand" "=r")
-       (xor:SI (match_operand:SI 1 "s_register_operand" "r")
-               (match_operand:SI 2 "arm_rhs_operand" "rI")))]
+(define_insn_and_split "*arm_xorsi3"
+  [(set (match_operand:SI         0 "s_register_operand" "=r,r")
+       (xor:SI (match_operand:SI 1 "s_register_operand" "%r,r")
+               (match_operand:SI 2 "reg_or_int_operand" "rI,?n")))]
   "TARGET_32BIT"
-  "eor%?\\t%0, %1, %2"
-  [(set_attr "predicable" "yes")]
+  "@
+   eor%?\\t%0, %1, %2
+   #"
+  "TARGET_32BIT
+   && GET_CODE (operands[2]) == CONST_INT
+   && !const_ok_for_arm (INTVAL (operands[2]))"
+  [(clobber (const_int 0))]
+{
+  arm_split_constant (XOR, SImode, curr_insn,
+                      INTVAL (operands[2]), operands[0], operands[1], 0);
+  DONE;
+}
+  [(set_attr "length" "4,16")
+   (set_attr "predicable" "yes")]
 )
 
 (define_insn "*thumb1_xorsi3_insn"