arch:dts:starfive:Modify i2stx_4ch0 node

Add mclk_ext clock and enable i2stx_4ch0 status.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>

diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
old mode 100755 (executable)
new mode 100644 (file)
index bd9cedb..50d926d
--- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
@@ -7,6 +7,7 @@
 /dts-v1/;
 #include "jh7110.dtsi"
 #include "jh7110-evb-pinctrl.dtsi"
+#include "codecs/sf_hdmi.dtsi"
 
 / {
        aliases {
@@ -430,7 +431,7 @@
 
 &spdif0 {
        pinctrl-names = "default";
-       pinctrl-0 = <&spdif0_pins &mclk_ext_pins>;
+       pinctrl-0 = <&spdif0_pins>;
        status = "disabled";
 };
 
@@ -446,7 +447,7 @@
 
 &pdm {
        pinctrl-names = "default";
-       pinctrl-0 = <&pdm0_pins &mclk_ext_pins>;
+       pinctrl-0 = <&pdm0_pins>;
        status = "disabled";
 };
 
@@ -463,7 +464,9 @@
 };
 
 &i2stx_4ch0 {
-       status = "disabled";
+       pinctrl-names = "default";
+       pinctrl-0 = <&mclk_ext_pins>;
+       status = "okay";
 };
 
 &i2stx_4ch1 {

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
old mode 100755 (executable)
new mode 100644 (file)
index 8df9300..945d3e7
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -1293,19 +1293,23 @@
                };
 
                i2stx_4ch0: i2stx_4ch0@120b0000 {
-                       compatible = "snps,designware-i2stx-4ch0";
+                       compatible = "starfive,jh7110-i2stx-4ch0", "snps,designware-i2s";
                        reg = <0x0 0x120b0000 0x0 0x1000>;
                        clocks = <&clkgen JH7110_MCLK_INNER>,
                                 <&clkgen JH7110_I2STX_4CH0_BCLK_MST>,
                                 <&clkgen JH7110_I2STX_4CH0_LRCK_MST>,
                                 <&clkgen JH7110_MCLK>,
                                 <&clkgen JH7110_I2STX0_4CHBCLK>,
-                                <&clkgen JH7110_I2STX0_4CHLRCK>;
+                                <&clkgen JH7110_I2STX0_4CHLRCK>,
+                                <&clkgen JH7110_I2STX0_4CHCLK_APB>,
+                                <&mclk_ext>;
                        clock-names = "inner", "bclk-mst",
                                        "lrck-mst", "mclk",
-                                       "bclk0", "lrck0";
+                                       "bclk0", "lrck0",
+                                       "i2s_apb", "mclk_ext";
                        resets = <&rstgen RSTN_U0_I2STX_4CH_APB>,
                                 <&rstgen RSTN_U0_I2STX_4CH_BCLK>;
+                       reset-names = "rst_apb", "rst_bclk";
                        dmas = <&dma 47 1>;
                        dma-names = "tx";
                        #sound-dai-cells = <0>;