mpc85xx/t2081: enable parsing DDR ratio for T2081 rev1.1
authorShengzhou Liu <Shengzhou.Liu@freescale.com>
Mon, 26 Oct 2015 05:51:58 +0000 (13:51 +0800)
committerYork Sun <yorksun@freescale.com>
Mon, 2 Nov 2015 16:51:50 +0000 (08:51 -0800)
T2081 rev 1.1 changes MEM_PLL_RAT in RCW which requires new parsing
for PLL ratio.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
arch/powerpc/cpu/mpc85xx/speed.c

index d954fe2..e732969 100644 (file)
@@ -131,7 +131,8 @@ void get_sys_info(sys_info_t *sys_info)
         * T2080 rev 1.1 and later also use half mem_pll comparing with rev 1.0
         */
 #if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
-       defined(CONFIG_PPC_T4080) || defined(CONFIG_PPC_T2080)
+       defined(CONFIG_PPC_T4080) || defined(CONFIG_PPC_T2080) || \
+       defined(CONFIG_PPC_T2081)
        svr = get_svr();
        switch (SVR_SOC_VER(svr)) {
        case SVR_T4240: