Use Cortex-A17 tuning parameters for Cortex-A12

	* config/arm/arm.c (arm_cortex_a12_tune): Update entries to match
	Cortex-A17 tuning parameters.
	* config/arm/arm-cores.def (cortex-a12): Schedule for cortex-a17.

Change-Id: I052388833c5c3f988665a8abc4ffa5a5b873d586
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@219472 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def
index 423ee9e..637be15 100644 (file)
--- a/gcc/config/arm/arm-cores.def
+++ b/gcc/config/arm/arm-cores.def
@@ -148,7 +148,7 @@ ARM_CORE("cortex-a5",               cortexa5, cortexa5,             7A,  FL_LDSCHED, cortex_a5)
 ARM_CORE("cortex-a7",          cortexa7, cortexa7,             7A,  FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a7)
 ARM_CORE("cortex-a8",          cortexa8, cortexa8,             7A,  FL_LDSCHED, cortex_a8)
 ARM_CORE("cortex-a9",          cortexa9, cortexa9,             7A,  FL_LDSCHED, cortex_a9)
-ARM_CORE("cortex-a12",         cortexa12, cortexa15,           7A,  FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a12)
+ARM_CORE("cortex-a12",         cortexa12, cortexa17,           7A,  FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a12)
 ARM_CORE("cortex-a15",         cortexa15, cortexa15,           7A,  FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a15)
 ARM_CORE("cortex-a17",         cortexa17, cortexa17,           7A,  FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a12)
 ARM_CORE("cortex-r4",          cortexr4, cortexr4,             7R,  FL_LDSCHED, cortex)

diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 8a9f20b..1b3163a 100644 (file)
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -1938,17 +1938,17 @@ const struct tune_params arm_cortex_a12_tune =
 {
   arm_9e_rtx_costs,
   &cortexa12_extra_costs,
-  NULL,
+  NULL,                                                /* Sched adj cost.  */
   1,                                           /* Constant limit.  */
-  5,                                           /* Max cond insns.  */
-  ARM_PREFETCH_BENEFICIAL(4,32,32),
+  2,                                           /* Max cond insns.  */
+  ARM_PREFETCH_NOT_BENEFICIAL,
   false,                                       /* Prefer constant pool.  */
   arm_default_branch_cost,
   true,                                                /* Prefer LDRD/STRD.  */
   {true, true},                                        /* Prefer non short circuit.  */
   &arm_default_vec_cost,                        /* Vectorizer costs.  */
   false,                                        /* Prefer Neon for 64-bits bitops.  */
-  false, false                                  /* Prefer 32-bit encodings.  */
+  true, true,                                   /* Prefer 32-bit encodings.  */
 };
 
 /* armv7m tuning.  On Cortex-M4 cores for example, MOVW/MOVT take a single