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zynq: Update CLK in bdinfo
author
Michal Simek
<michal.simek@xilinx.com>
Mon, 20 Jan 2014 10:05:37 +0000
(11:05 +0100)
committer
Michal Simek
<michal.simek@xilinx.com>
Wed, 19 Feb 2014 08:41:22 +0000
(09:41 +0100)
ARM has specific clk entries which should be also setup.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
arch/arm/cpu/armv7/zynq/clk.c
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diff --git
a/arch/arm/cpu/armv7/zynq/clk.c
b/arch/arm/cpu/armv7/zynq/clk.c
index
4307111
..
d2885dc
100644
(file)
--- a/
arch/arm/cpu/armv7/zynq/clk.c
+++ b/
arch/arm/cpu/armv7/zynq/clk.c
@@
-161,6
+161,8
@@
static void init_ddr_clocks(void)
clks[dci_clk].frequency = DIV_ROUND_CLOSEST(
DIV_ROUND_CLOSEST(prate, div0), div1);
clks[dci_clk].name = "dci";
+
+ gd->bd->bi_ddr_freq = clks[ddr3x_clk].frequency / 1000000;
}
static void init_cpu_clocks(void)
@@
-593,6
+595,9
@@
int set_cpu_clk_info(void)
init_periph_clocks();
init_aper_clocks();
+ gd->bd->bi_arm_freq = gd->cpu_clk / 1000000;
+ gd->bd->bi_dsp_freq = 0;
+
return 0;
}