switch (N->getOpcode()) {
default: llvm_unreachable("Unexpected opcode!");
+ case X86ISD::ANDNP:
+ if (A == N0)
+ Imm &= ~TernlogMagicA;
+ else
+ Imm = ~(Imm) & TernlogMagicA;
+ break;
case ISD::AND: Imm &= TernlogMagicA; break;
case ISD::OR: Imm |= TernlogMagicA; break;
case ISD::XOR: Imm ^= TernlogMagicA; break;
return;
break;
+ case X86ISD::ANDNP:
+ if (tryVPTERNLOG(Node))
+ return;
+ break;
+
case ISD::AND:
if (NVT.isVector() && NVT.getVectorElementType() == MVT::i1) {
// Try to form a masked VPTESTM. Operands can be in either order.
define <4 x i32> @ternlog_andn_or(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z) {
; CHECK-LABEL: ternlog_andn_or:
; CHECK: ## %bb.0:
-; CHECK-NEXT: vorps %xmm2, %xmm1, %xmm1
-; CHECK-NEXT: vandnps %xmm1, %xmm0, %xmm0
+; CHECK-NEXT: vpternlogd $14, %xmm2, %xmm1, %xmm0
; CHECK-NEXT: retq
%a = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
%b = or <4 x i32> %y, %z
define <4 x i32> @ternlog_andn_or_2(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z) {
; CHECK-LABEL: ternlog_andn_or_2:
; CHECK: ## %bb.0:
-; CHECK-NEXT: vorps %xmm2, %xmm1, %xmm1
-; CHECK-NEXT: vandnps %xmm0, %xmm1, %xmm0
+; CHECK-NEXT: vpternlogd $16, %xmm2, %xmm1, %xmm0
; CHECK-NEXT: retq
%a = or <4 x i32> %y, %z
%b = xor <4 x i32> %a, <i32 -1, i32 -1, i32 -1, i32 -1>