edma_write_array2(j, EDMA_DRAE, i, 1, 0x0);
edma_write_array(j, EDMA_QRAE, i, 0x0);
}
+
+ edma_cc[j]->info = info[j];
++
+ dmaengine_pdev = platform_device_register_full(
+ &edma_dmaengine_dev[j]);
+ if (IS_ERR(dmaengine_pdev))
+ dev_err(dev,
+ "device%d for dmaengine register failed (%ld)",
+ j, PTR_ERR(dmaengine_pdev));
+
arch_num_cc++;
}
#include <linux/clkdev.h>
#include <linux/clk/ti.h>
- #define DRA7_DPLL_ABE_DEFFREQ 361267200
+ #define DRA7_DPLL_ABE_DEFFREQ 180633600
#define DRA7_DPLL_GMAC_DEFFREQ 1000000000
+#define DRA7_DPLL_DSP_DEFFREQ 600000000
+#define DRA7_DPLL_DSP_GFCLK_NOMFREQ 600000000
+#define DRA7_DPLL_EVE_GCLK_NOMFREQ 400000000
+
+ #define DRA7_ATL_DEFFREQ 5644800
static struct ti_dt_clk dra7xx_clks[] = {
DT_CLK(NULL, "atl_clkin0_ck", "atl_clkin0_ck"),
{
int rc;
struct clk *abe_dpll_mux, *sys_clkin2, *dpll_ck, *dss_deshdcp_ck;
+ struct clk *ipu1_gfclk, *ipu1_gfclk_parent;
+ struct clk *dsp_dpll, *dsp_m2_dpll, *dsp_m3x2_dpll;
+ struct clk *atl_fck, *atl_parent;
ti_dt_clocks_register(dra7xx_clks);
if (rc)
pr_err("%s: failed to enable DESHDCP clock\n", __func__);
+ ipu1_gfclk = clk_get_sys(NULL, "ipu1_gfclk_mux");
+ ipu1_gfclk_parent = clk_get_sys(NULL, "dpll_core_h22x2_ck");
+ rc = clk_set_parent(ipu1_gfclk, ipu1_gfclk_parent);
+ if (rc)
+ pr_err("%s: failed to reparent ipu1_gfclk_mux\n", __func__);
+
+ dsp_dpll = clk_get_sys(NULL, "dpll_dsp_ck");
+ rc = clk_set_rate(dsp_dpll, DRA7_DPLL_DSP_DEFFREQ);
+ if (!rc) {
+ dsp_m2_dpll = clk_get_sys(NULL, "dpll_dsp_m2_ck");
+ rc = clk_set_rate(dsp_m2_dpll, DRA7_DPLL_DSP_GFCLK_NOMFREQ);
+ if (rc)
+ pr_err("%s: failed to configure DSP DPLL m2 output!\n",
+ __func__);
+
+ dsp_m3x2_dpll = clk_get_sys(NULL, "dpll_dsp_m3x2_ck");
+ rc = clk_set_rate(dsp_m3x2_dpll, DRA7_DPLL_EVE_GCLK_NOMFREQ);
+ if (rc)
+ pr_err("%s: failed to configure DSP DPLL m3x2 divider!\n",
+ __func__);
+ } else {
+ pr_err("%s: failed to configure DSP DPLL!\n", __func__);
+ }
+
+ atl_fck = clk_get_sys(NULL, "atl_gfclk_mux");
+ atl_parent = clk_get_sys(NULL, "dpll_abe_m2_ck");
+ rc = clk_set_parent(atl_fck, atl_parent);
+ if (rc)
+ pr_err("%s: failed to reparent atl_gfclk_mux\n", __func__);
+
+ atl_fck = clk_get_sys(NULL, "atl_clkin2_ck");
+ rc = clk_set_rate(atl_fck, DRA7_ATL_DEFFREQ);
+ if (rc)
+ pr_err("%s: failed to set atl_clkin2_ck\n", __func__);
+
+ atl_fck = clk_get_sys(NULL, "atl_clkin1_ck");
+ rc = clk_set_rate(atl_fck, DRA7_ATL_DEFFREQ);
+ if (rc)
+ pr_err("%s: failed to set atl_clkin1_ck\n", __func__);
+
return rc;
}