accessed */ \
target_ulong mem_io_vaddr; /* target virtual addr at which the \
memory was accessed */ \
- int halted; /* TRUE if the CPU is in suspend state */ \
+ uint32_t halted; /* Nonzero if the CPU is in suspend state */ \
+ uint32_t interrupt_request; \
/* The meaning of the MMU modes is defined in the target code. */ \
CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \
target_phys_addr_t iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \
jmp_buf jmp_env; \
int exception_index; \
\
+ int user_mode_only; \
+ \
void *next_cpu; /* next CPU sharing TB cache */ \
int cpu_index; /* CPU index (informative) */ \
int running; /* Nonzero if cpu is currently running(usermode). */ \
#endif
}
+#if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY)
+
+#define CPU_COMMON_SAVE_VERSION 1
+
+static void cpu_common_save(QEMUFile *f, void *opaque)
+{
+ CPUState *env = opaque;
+
+ qemu_put_be32s(f, &env->halted);
+ qemu_put_be32s(f, &env->interrupt_request);
+}
+
+static int cpu_common_load(QEMUFile *f, void *opaque, int version_id)
+{
+ CPUState *env = opaque;
+
+ if (version_id != CPU_COMMON_SAVE_VERSION)
+ return -EINVAL;
+
+ qemu_get_be32s(f, &env->halted);
+ qemu_put_be32s(f, &env->interrupt_request);
+ tlb_flush(env, 1);
+
+ return 0;
+}
+#endif
+
void cpu_exec_init(CPUState *env)
{
CPUState **penv;
env->nb_watchpoints = 0;
*penv = env;
#if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY)
+ register_savevm("cpu_common", cpu_index, CPU_COMMON_SAVE_VERSION,
+ cpu_common_save, cpu_common_load, env);
register_savevm("cpu", cpu_index, CPU_SAVE_VERSION,
cpu_save, cpu_load, env);
#endif
/* Those resources are used only in Qemu core */
CPU_COMMON
- int user_mode_only; /* user mode only simulation */
uint32_t hflags;
int error_code;
- int interrupt_request;
uint32_t features;
uint32_t amask;
int (*get_irq_vector)(struct CPUARMState *);
void *irq_opaque;
- /* exception/interrupt handling */
- int interrupt_request;
- int user_mode_only;
-
/* VFP coprocessor state. */
struct {
float64 regs[32];
/* X flag at the time of cc snapshot. */
int cc_x;
- int interrupt_request;
int interrupt_vector;
int fault_vector;
int trap_vector;
uint32_t lo;
} tlbsets[2][4][16];
- int user_mode_only;
-
CPU_COMMON
} CPUCRISState;
target_ulong exception_next_eip;
target_ulong dr[8]; /* debug registers */
uint32_t smbase;
- int interrupt_request;
- int user_mode_only; /* user mode only simulation */
int old_exception; /* exception in flight */
CPU_COMMON
#define cpu_signal_handler cpu_x86_signal_handler
#define cpu_list x86_cpu_list
-#define CPU_SAVE_VERSION 5
+#define CPU_SAVE_VERSION 6
/* MMU modes definitions */
#define MMU_MODE0_SUFFIX _kernel
qemu_put_be64s(f, &env->pat);
qemu_put_be32s(f, &env->hflags2);
- qemu_put_be32s(f, (uint32_t *)&env->halted);
qemu_put_be64s(f, &env->vm_hsave);
qemu_put_be64s(f, &env->vm_vmcb);
uint16_t fpus, fpuc, fptag, fpregs_format;
int32_t a20_mask;
- if (version_id != 3 && version_id != 4 && version_id != 5)
+ if (version_id != 3 && version_id != 4 && version_id != 5
+ && version_id != 6)
return -EINVAL;
for(i = 0; i < CPU_NB_REGS; i++)
qemu_get_betls(f, &env->regs[i]);
if (version_id >= 5) {
qemu_get_be64s(f, &env->pat);
qemu_get_be32s(f, &env->hflags2);
- qemu_get_be32s(f, (uint32_t *)&env->halted);
+ if (version_id < 6)
+ qemu_get_be32s(f, &env->halted);
qemu_get_be64s(f, &env->vm_hsave);
qemu_get_be64s(f, &env->vm_vmcb);
/* ??? remove this. */
uint32_t t1;
- /* exception/interrupt handling */
- int interrupt_request;
- int user_mode_only;
-
int pending_vector;
int pending_level;
/* We waste some space so we can handle shadow registers like TCs. */
TCState tcs[MIPS_SHADOW_SET_MAX];
/* Qemu */
- int interrupt_request;
int error_code;
- int user_mode_only; /* user mode only simulation */
uint32_t hflags; /* CPU State */
/* TMASK defines different execution modes */
#define MIPS_HFLAG_TMASK 0x01FF
uint32_t flags;
int error_code;
- int interrupt_request;
uint32_t pending_interrupts;
#if !defined(CONFIG_USER_ONLY)
/* This is the IRQ controller, which is implementation dependant
opc_handler_t *opcodes[0x40];
/* Those resources are used only in Qemu core */
- int user_mode_only; /* user mode only simulation */
target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */
target_ulong hflags_nmsr; /* specific hflags, not comming from MSR */
int mmu_idx; /* precomputed MMU index to speed up mem accesses */
uint32_t expevt; /* exception event register */
uint32_t intevt; /* interrupt event register */
- int user_mode_only;
- int interrupt_request;
CPU_COMMON tlb_t utlb[UTLB_SIZE]; /* unified translation table */
tlb_t itlb[ITLB_SIZE]; /* instruction translation table */
void *intc_handle;
uint32_t pil_in; /* incoming interrupt level bitmap */
int psref; /* enable fpu */
target_ulong version;
- int user_mode_only;
int interrupt_index;
- int interrupt_request;
uint32_t mmu_bm;
uint32_t mmu_ctpr_mask;
uint32_t mmu_cxr_mask;