s5j: use get/putreg32 when acceessing SFR

This commit replaces all usages of HW_REG32() and __raw_read/writel()
macro with get/putreg32() for better readability and consistency. This
commit alters quite a lot, but does not make functional differences.

Change-Id: I9a3646737efd5ab7cc4e7e5d9ccffbb6b0402954
Signed-off-by: Heesub Shin <heesub.shin@samsung.com>

diff --git a/os/arch/arm/src/s5j/s5j_gpio.c b/os/arch/arm/src/s5j/s5j_gpio.c
index ee54069..aa50b7a 100644 (file)
--- a/os/arch/arm/src/s5j/s5j_gpio.c
+++ b/os/arch/arm/src/s5j/s5j_gpio.c
@@ -885,11 +885,11 @@ int gpio_cfg_pin(int gpio, int cfg)
 
        port = s5j_gpio_port(gpio);
 
-       value = __raw_readl(gb->base + GPIO_CON);
+       value = getreg32(gb->base + GPIO_CON);
        value &= ~CON_MASK(port);
        value |= CON_SFR(port, cfg);
 
-       __raw_writel(value, gb->base + GPIO_CON);
+       putreg32(value, gb->base + GPIO_CON);
 
        return 0;
 }
@@ -924,7 +924,7 @@ int gpio_cfg_get_pin(int gpio)
 
        port = s5j_gpio_port(gpio);
 
-       value = __raw_readl(gb->base + GPIO_CON);
+       value = getreg32(gb->base + GPIO_CON);
 
        return ((value >> (port << 2)) & 0xF);
 }
@@ -957,13 +957,13 @@ int gpio_direction_output(int gpio, int high)
 
        port = s5j_gpio_port(gpio);
 
-       value = __raw_readl(gb->base + GPIO_DAT);
+       value = getreg32(gb->base + GPIO_DAT);
        value &= ~(1 << port);
        if (high) {
                value |= (1 << port);
        }
 
-       __raw_writel(value, gb->base + GPIO_DAT);
+       putreg32(value, gb->base + GPIO_DAT);
 
        return gpio_cfg_pin(gpio, GPIO_OUTPUT);
 }
@@ -1014,13 +1014,13 @@ int gpio_set_value(int gpio, int high)
 
        port = s5j_gpio_port(gpio);
 
-       value = __raw_readl(gb->base + GPIO_DAT);
+       value = getreg32(gb->base + GPIO_DAT);
        value &= ~(1 << port);
        if (high) {
                value |= (1 << port);
        }
 
-       __raw_writel(value, gb->base + GPIO_DAT);
+       putreg32(value, gb->base + GPIO_DAT);
 
        return 0;
 }
@@ -1053,7 +1053,7 @@ int gpio_get_value(int gpio)
 
        port = s5j_gpio_port(gpio);
 
-       value = __raw_readl(gb->base + GPIO_DAT);
+       value = getreg32(gb->base + GPIO_DAT);
 
        return (value >> port) & 1;
 }
@@ -1085,7 +1085,7 @@ int gpio_set_pull(int gpio, int mode)
 
        port = s5j_gpio_port(gpio);
 
-       value = __raw_readl(gb->base + GPIO_PUD);
+       value = getreg32(gb->base + GPIO_PUD);
        value &= ~PULL_MASK(port);
 
        switch (mode) {
@@ -1100,7 +1100,7 @@ int gpio_set_pull(int gpio, int mode)
                return -EINVAL;
        }
 
-       __raw_writel(value, gb->base + GPIO_PUD);
+       putreg32(value, gb->base + GPIO_PUD);
 
        return 0;
 }
@@ -1131,7 +1131,7 @@ int gpio_get_pull(int gpio)
 
        port = s5j_gpio_port(gpio);
 
-       value = __raw_readl(gb->base + GPIO_PUD);
+       value = getreg32(gb->base + GPIO_PUD);
        value &= PULL_MASK(port);
 
        return value;
@@ -1163,7 +1163,7 @@ int gpio_set_drv(int gpio, int mode)
 
        port = s5j_gpio_port(gpio);
 
-       value = __raw_readl(gb->base + GPIO_DRVSR);
+       value = getreg32(gb->base + GPIO_DRVSR);
        value &= ~DRV_MASK(port);
 
        switch (mode) {
@@ -1177,7 +1177,7 @@ int gpio_set_drv(int gpio, int mode)
                return -EINVAL;
        }
 
-       __raw_writel(value, gb->base + GPIO_DRVSR);
+       putreg32(value, gb->base + GPIO_DRVSR);
 
        return 0;
 }
@@ -1207,7 +1207,7 @@ int gpio_get_drv(int gpio)
 
        port = s5j_gpio_port(gpio);
 
-       value = __raw_readl(gb->base + GPIO_DRVSR);
+       value = getreg32(gb->base + GPIO_DRVSR);
        value &= ~DRV_MASK(port);
 
        return value;
@@ -1239,7 +1239,7 @@ int gpio_set_rate(int gpio, int mode)
 
        port = s5j_gpio_port(gpio);
 
-       value = __raw_readl(gb->base + GPIO_DRVSR);
+       value = getreg32(gb->base + GPIO_DRVSR);
        value &= ~RATE_MASK(port);
 
        switch (mode) {
@@ -1251,7 +1251,7 @@ int gpio_set_rate(int gpio, int mode)
                return -EINVAL;
        }
 
-       __raw_writel(value, gb->base + GPIO_DRVSR);
+       putreg32(value, gb->base + GPIO_DRVSR);
 
        return 0;
 }
@@ -1282,11 +1282,11 @@ int gpio_cfg_pin_pdn(int gpio, int cfg)
 
        port = s5j_gpio_port(gpio);
 
-       value = __raw_readl(gb->base + GPIO_CONPDN);
+       value = getreg32(gb->base + GPIO_CONPDN);
        value &= ~CONPDN_MASK(port);
        value |= CONPDN_SFR(port, cfg);
 
-       __raw_writel(value, gb->base + GPIO_CONPDN);
+       putreg32(value, gb->base + GPIO_CONPDN);
 
        return 0;
 }
@@ -1318,7 +1318,7 @@ int gpio_set_pull_pdn(int gpio, int mode)
 
        port = s5j_gpio_port(gpio);
 
-       value = __raw_readl(gb->base + GPIO_PUDPDN);
+       value = getreg32(gb->base + GPIO_PUDPDN);
        value &= ~PUDPDN_MASK(port);
 
        switch (mode) {
@@ -1330,7 +1330,7 @@ int gpio_set_pull_pdn(int gpio, int mode)
                return -EINVAL;
        }
 
-       __raw_writel(value, gb->base + GPIO_PUDPDN);
+       putreg32(value, gb->base + GPIO_PUDPDN);
 
        return 0;
 }
@@ -1362,9 +1362,9 @@ int gpio_eint_mask(int gpio)
        port = s5j_gpio_port(gpio);
        eint_addr = __gpio_eint_get_addr(gpio, GPIO_EINT_MASK);
 
-       mask = __raw_readl(eint_addr);
+       mask = getreg32(eint_addr);
        mask |= 1 << port;
-       __raw_writel(mask, eint_addr);
+       putreg32(mask, eint_addr);
 
        return 0;
 }
@@ -1395,9 +1395,9 @@ int gpio_eint_unmask(int gpio)
        port = s5j_gpio_port(gpio);
        eint_addr = __gpio_eint_get_addr(gpio, GPIO_EINT_MASK);
 
-       mask = __raw_readl(eint_addr);
+       mask = getreg32(eint_addr);
        mask &= ~(1 << port);
-       __raw_writel(mask, eint_addr);
+       putreg32(mask, eint_addr);
 
        return 0;
 }
@@ -1424,7 +1424,7 @@ bool gpio_eint_ispending(int gpio)
        port = s5j_gpio_port(gpio);
        eint_addr = __gpio_eint_get_addr(gpio, GPIO_EINT_PEND);
 
-       pend = __raw_readl(eint_addr);
+       pend = getreg32(eint_addr);
 
        return (pend & (1 << port)) ? true : false;
 }
@@ -1462,9 +1462,9 @@ int gpio_eint_clear_pending(int gpio)
        port = s5j_gpio_port(gpio);
        eint_addr = __gpio_eint_get_addr(gpio, GPIO_EINT_PEND);
 
-       pend = __raw_readl(eint_addr);
+       pend = getreg32(eint_addr);
        pend &= 1 << port;
-       __raw_writel(pend, eint_addr);
+       putreg32(pend, eint_addr);
 
        return 0;
 }
@@ -1502,9 +1502,9 @@ int gpio_eint_enable_filter(int gpio)
                shift_port = 8 * (port - 4);
        }
 
-       filter_con = __raw_readl(eint_addr);
+       filter_con = getreg32(eint_addr);
        filter_con |= (1 << 7) << shift_port;
-       __raw_writel(filter_con, eint_addr);
+       putreg32(filter_con, eint_addr);
 
        return 0;
 }
@@ -1542,9 +1542,9 @@ int gpio_eint_disable_filter(int gpio)
                shift_port = 8 * (port - 4);
        }
 
-       filter_con = __raw_readl(eint_addr);
+       filter_con = getreg32(eint_addr);
        filter_con &= ~((1 << 7) << shift_port);
-       __raw_writel(filter_con, eint_addr);
+       putreg32(filter_con, eint_addr);
 
        return 0;
 }
@@ -1594,7 +1594,7 @@ int gpio_eint_set_filter(int gpio, unsigned type, unsigned width)
                shift_port = 8 * (port - 4);
        }
 
-       filter_con = __raw_readl(eint_addr);
+       filter_con = getreg32(eint_addr);
 
        if (bank < 4) {                         /* Alive Filter Setting */
                if (type == EINT_FILTER_DELAY) {
@@ -1613,7 +1613,7 @@ int gpio_eint_set_filter(int gpio, unsigned type, unsigned width)
                filter_con &= ~(0x7f << shift_port);
                filter_con |= width << shift_port;
        }
-       __raw_writel(filter_con, eint_addr);
+       putreg32(filter_con, eint_addr);
 
        return 0;
 }
@@ -1658,10 +1658,10 @@ int gpio_eint_set_type(int gpio, unsigned type)
        port = s5j_gpio_port(gpio);
        eint_addr = __gpio_eint_get_addr(gpio, GPIO_EINT_CON);
        mask = 0x7 << (port * 4);
-       ctrl = __raw_readl(eint_addr);
+       ctrl = getreg32(eint_addr);
        ctrl &= ~mask;
        ctrl |= type << (port * 4);
-       __raw_writel(ctrl, eint_addr);
+       putreg32(ctrl, eint_addr);
 
        if (gpio_eint_ispending(gpio)) {
                gpio_eint_clear_pending(gpio);
@@ -1696,7 +1696,7 @@ int gpio_eint_get_type(int gpio)
        port = s5j_gpio_port(gpio);
        eint_addr = __gpio_eint_get_addr(gpio, GPIO_EINT_CON);
        mask = 0x7 << (port * 4);
-       ctrl = __raw_readl(eint_addr);
+       ctrl = getreg32(eint_addr);
        ctrl &= mask;
        ctrl = ctrl >> (port * 4);
 

diff --git a/os/arch/arm/src/s5j/s5j_pwrcal.c b/os/arch/arm/src/s5j/s5j_pwrcal.c
index ae0149b..0df232b 100644 (file)
--- a/os/arch/arm/src/s5j/s5j_pwrcal.c
+++ b/os/arch/arm/src/s5j/s5j_pwrcal.c
@@ -101,7 +101,7 @@ int cal_clk_setrate(unsigned int id, unsigned long rate)
                /* CLK_CON_DIV_DIV_CLK_SERIALFLASH */
                parents = 320000000;
                div = parents / rate;
-               SetBits(0x80081800, 0, 0xF, (div - 1));
+               modifyreg32(0x80081800, 0xf, (div - 1));
                break;
        default:
                break;

diff --git a/os/arch/arm/src/s5j/s5j_serial.c b/os/arch/arm/src/s5j/s5j_serial.c
index 0222acf..8ed878b 100644 (file)
--- a/os/arch/arm/src/s5j/s5j_serial.c
+++ b/os/arch/arm/src/s5j/s5j_serial.c
@@ -470,14 +470,14 @@ void up_uart_set_gpio(UART_CHANNEL eCh)
 static void up_uart_enable_interrupt(uint32_t uBase, UART_INTERRUPT eInt)
 {
        if (eInt & ERROR_INT) {
-               HW_REG32(uBase, UART_CON) |= (0x1 << 6);
+               modifyreg32(uBase + UART_CON, 0, (0x1 << 6));
        }
 
        if (eInt & MODEM_INT) {
-               HW_REG32(uBase, UART_MCON) |= (0x1 << 3);
+               modifyreg32(uBase + UART_MCON, 0, (0x1 << 3));
        }
 
-       HW_REG32(uBase, UART_INTM) &= ~(eInt);
+       modifyreg32(uBase + UART_INTM, eInt, 0);
 }
 
 /****************************************************************************
@@ -495,14 +495,14 @@ static void up_uart_enable_interrupt(uint32_t uBase, UART_INTERRUPT eInt)
  ****************************************************************************/
 static void up_uart_disable_interrupt(uint32_t uBase, UART_INTERRUPT eInt)
 {
-       HW_REG32(uBase, UART_INTM) |= eInt;
+       modifyreg32(uBase + UART_INTM, 0, eInt);
 
        if (eInt & ERROR_INT) {
-               HW_REG32(uBase, UART_CON) &= ~(0x1 << 6);
+               modifyreg32(uBase + UART_CON, 0x1 << 6, 0);
        }
 
        if (eInt & MODEM_INT) {
-               HW_REG32(uBase, UART_MCON) &= ~(0x1 << 3);
+               modifyreg32(uBase + UART_MCON, 0x1 << 3, 0);
        }
 }
 
@@ -521,23 +521,23 @@ static void up_uart_disable_interrupt(uint32_t uBase, UART_INTERRUPT eInt)
  ****************************************************************************/
 static void up_uart_set_tx_mode(uint32_t uBase, UART_MODE eMode)
 {
-       HW_REG32(uBase, UART_CON) &= ~(0x3 << 2);
-       HW_REG32(uBase, UART_CON) &= ~(0x1 << 9);
+       modifyreg32(uBase + UART_CON, 0x3 << 2, 0);
+       modifyreg32(uBase + UART_CON, 0x1 << 9, 0);
        up_uart_disable_interrupt(uBase, TX_INT);       /*  Disable TX Interrupt */
 
        switch (eMode) {
        case POLL_MODE:
-               HW_REG32(uBase, UART_CON) |= (0x1 << 2);
+               modifyreg32(uBase + UART_CON, 0, 0x1 << 2);
                break;
 
        case INT_MODE:
-               HW_REG32(uBase, UART_CON) |= (0x1 << 2);
-               HW_REG32(uBase, UART_CON) |= (0x1 << 9);
+               modifyreg32(uBase + UART_CON, 0, 0x1 << 2);
+               modifyreg32(uBase + UART_CON, 0, 0x1 << 9);
                up_uart_enable_interrupt(uBase, TX_INT);        /*  Enable TX Interrupt */
                break;
 
        case DMA_MODE:
-               HW_REG32(uBase, UART_CON) |= (0x2 << 2);
+               modifyreg32(uBase + UART_CON, 0, 0x2 << 2);
                break;
 
        case DISABLE_MODE:
@@ -561,25 +561,25 @@ static void up_uart_set_tx_mode(uint32_t uBase, UART_MODE eMode)
  ****************************************************************************/
 static void up_uart_set_rx_mode(uint32_t uBase, UART_MODE eMode)
 {
-       HW_REG32(uBase, UART_CON) &= ~(0x3 << 0);
-       HW_REG32(uBase, UART_CON) &= ~(0x1 << 8);
+       modifyreg32(uBase + UART_CON, 0x3 << 0, 0);
+       modifyreg32(uBase + UART_CON, 0x1 << 8, 0);
        up_uart_disable_interrupt(uBase, (UART_INTERRUPT)(RX_INT | ERROR_INT));
 
        switch (eMode) {
        case POLL_MODE:
-               HW_REG32(uBase, UART_CON) |= (0x1 << 0);
+               modifyreg32(uBase + UART_CON, 0, 0x1 << 0);
                up_uart_enable_interrupt(uBase, ERROR_INT);
                break;
 
        case INT_MODE:
-               HW_REG32(uBase, UART_CON) |= (0x1 << 0);
-               HW_REG32(uBase, UART_CON) |= (0x1 << 8);
+               modifyreg32(uBase + UART_CON, 0, 0x1 << 0);
+               modifyreg32(uBase + UART_CON, 0, 0x1 << 8);
                up_uart_enable_interrupt(uBase, (UART_INTERRUPT)(RX_INT | ERROR_INT));
                break;
 
        case DMA_MODE:
-               HW_REG32(uBase, UART_CON) |= (0x2 << 0);
-               HW_REG32(uBase, UART_CON) |= (0x1 << 8);
+               modifyreg32(uBase + UART_CON, 0, 0x2 << 0);
+               modifyreg32(uBase + UART_CON, 0, 0x1 << 8);
                up_uart_enable_interrupt(uBase, (UART_INTERRUPT)(RX_INT | ERROR_INT));
                break;
 
@@ -611,8 +611,8 @@ static void up_uart_set_baudrate(uint32_t uBase, UART_BAUDRATE nBaudrate, u32 nC
        fDiv = ((float)nClock / (float)(nBaudrate * 16)) - 1.0;
        fFrac = (u32)(((fDiv - (s32) fDiv) * 16));
 
-       HW_REG32(uBase, UART_BRDIV) = (u32) fDiv;
-       HW_REG32(uBase, UART_FRACVAL) = (u32) fFrac;
+       putreg32(fDiv, uBase + UART_BRDIV);
+       putreg32(fFrac, uBase + UART_FRACVAL);
 }
 
 /****************************************************************************
@@ -631,9 +631,9 @@ static void up_uart_set_baudrate(uint32_t uBase, UART_BAUDRATE nBaudrate, u32 nC
 static void up_uart_set_infrared_mode(uint32_t uBase, bool bEnable)
 {
        if (bEnable) {
-               HW_REG32(uBase, UART_LCON) |= (0x1 << 6);
+               modifyreg32(uBase + UART_LCON, 0, 0x1 << 6);
        } else {
-               HW_REG32(uBase, UART_LCON) &= ~(0x1 << 6);
+               modifyreg32(uBase + UART_LCON, 0x1 << 6, 0);
        }
 }
 
@@ -652,8 +652,7 @@ static void up_uart_set_infrared_mode(uint32_t uBase, bool bEnable)
  ****************************************************************************/
 static void up_uart_set_parity_mode(uint32_t uBase, UART_PARITY_MODE eParityMode)
 {
-       HW_REG32(uBase, UART_LCON) &= ~(0x7 << 3);
-       HW_REG32(uBase, UART_LCON) |= (eParityMode << 3);
+       modifyreg32(uBase + UART_LCON, 0x7 << 3, eParityMode << 3);
 }
 
 /****************************************************************************
@@ -671,8 +670,7 @@ static void up_uart_set_parity_mode(uint32_t uBase, UART_PARITY_MODE eParityMode
  ****************************************************************************/
 static void up_uart_set_stop_bit(uint32_t uBase, UART_STOP_BIT eStopBit)
 {
-       HW_REG32(uBase, UART_LCON) &= ~(0x1 << 2);
-       HW_REG32(uBase, UART_LCON) |= (eStopBit << 2);
+       modifyreg32(uBase + UART_LCON, 0x1 << 2, eStopBit << 2);
 }
 
 /****************************************************************************
@@ -690,8 +688,7 @@ static void up_uart_set_stop_bit(uint32_t uBase, UART_STOP_BIT eStopBit)
  ****************************************************************************/
 static void up_uart_set_word_length(uint32_t uBase, UART_WORD_LENGTH eWordLen)
 {
-       HW_REG32(uBase, UART_LCON) &= ~(0x3 << 0);
-       HW_REG32(uBase, UART_LCON) |= (eWordLen << 0);
+       modifyreg32(uBase + UART_LCON, 0x3 << 0, eWordLen << 0);
 }
 
 /****************************************************************************
@@ -710,9 +707,9 @@ static void up_uart_set_word_length(uint32_t uBase, UART_WORD_LENGTH eWordLen)
 static void up_uart_set_loopback(uint32_t uBase, bool bEnable)
 {
        if (bEnable) {
-               HW_REG32(uBase, UART_CON) |= (0x1 << 5);
+               modifyreg32(uBase + UART_CON, 0, 0x1 << 5);
        } else {
-               HW_REG32(uBase, UART_CON) &= ~(0x1 << 5);
+               modifyreg32(uBase + UART_CON, 0x1 << 5, 0);
        }
 }
 
@@ -731,8 +728,7 @@ static void up_uart_set_loopback(uint32_t uBase, bool bEnable)
  ****************************************************************************/
 static void up_uart_set_rx_timeout_interval(uint32_t uBase, u32 nTime)
 {
-       HW_REG32(uBase, UART_CON) &= ~(0xF << 12);
-       HW_REG32(uBase, UART_CON) |= ((nTime & 0xF) << 12);
+       modifyreg32(uBase + UART_CON, 0xf << 12, (nTime & 0xf) << 12);
 }
 
 /****************************************************************************
@@ -751,9 +747,9 @@ static void up_uart_set_rx_timeout_interval(uint32_t uBase, u32 nTime)
 static void up_uart_set_rx_timeout(uint32_t uBase, bool bEnable)
 {
        if (bEnable) {
-               HW_REG32(uBase, UART_CON) |= (0x1 << 7);
+               modifyreg32(uBase + UART_CON, 0, 0x1 << 7);
        } else {
-               HW_REG32(uBase, UART_CON) &= ~(0x1 << 7);
+               modifyreg32(uBase + UART_CON, 0x1 << 7, 0);
        }
 }
 
@@ -773,9 +769,9 @@ static void up_uart_set_rx_timeout(uint32_t uBase, bool bEnable)
 static void up_uart_set_rx_timeout_with_empty_rx_fifo(uint32_t uBase, bool bEnable)
 {
        if (bEnable) {
-               HW_REG32(uBase, UART_CON) |= (0x1 << 11);
+               modifyreg32(uBase + UART_CON, 0, 0x1 << 11);
        } else {
-               HW_REG32(uBase, UART_CON) &= ~(0x1 << 11);
+               modifyreg32(uBase + UART_CON, 0x1 << 11, 0);
        }
 }
 
@@ -795,9 +791,9 @@ static void up_uart_set_rx_timeout_with_empty_rx_fifo(uint32_t uBase, bool bEnab
 static void up_uart_set_rx_timeout_suspend_dma(uint32_t uBase, bool bEnable)
 {
        if (bEnable) {
-               HW_REG32(uBase, UART_CON) |= (0x1 << 10);
+               modifyreg32(uBase + UART_CON, 0, 0x1 << 10);
        } else {
-               HW_REG32(uBase, UART_CON) &= ~(0x1 << 10);
+               modifyreg32(uBase + UART_CON, 0x1 << 10, 0);
        }
 }
 
@@ -816,12 +812,12 @@ static void up_uart_set_rx_timeout_suspend_dma(uint32_t uBase, bool bEnable)
  ****************************************************************************/
 static void up_uart_set_fifo_mode(uint32_t uBase, bool bEnable)
 {
-       HW_REG32(uBase, UART_FCON) |= (0x3 << 1);
+       modifyreg32(uBase + UART_FCON, 0, 0x3 << 1);
 
        if (bEnable) {
-               HW_REG32(uBase, UART_FCON) |= (0x1 << 0);
+               modifyreg32(uBase + UART_FCON, 0, 0x1 << 0);
        } else {
-               HW_REG32(uBase, UART_FCON) &= ~(0x1 << 0);
+               modifyreg32(uBase + UART_FCON, 0x1 << 0, 0);
        }
 }
 
@@ -840,8 +836,7 @@ static void up_uart_set_fifo_mode(uint32_t uBase, bool bEnable)
  ****************************************************************************/
 static void up_uart_set_tx_trigger_level(uint32_t uBase, UART_TRIGGER_LEVEL eTriggerLevel)
 {
-       HW_REG32(uBase, UART_FCON) &= ~(0x7 << 8);
-       HW_REG32(uBase, UART_FCON) |= (eTriggerLevel << 8);
+       modifyreg32(uBase + UART_FCON, 0x7 << 8, eTriggerLevel << 8);
 }
 
 /****************************************************************************
@@ -859,8 +854,7 @@ static void up_uart_set_tx_trigger_level(uint32_t uBase, UART_TRIGGER_LEVEL eTri
  ****************************************************************************/
 static void up_uart_set_rx_trigger_level(uint32_t uBase, UART_TRIGGER_LEVEL eTriggerLevel)
 {
-       HW_REG32(uBase, UART_FCON) &= ~(0x7 << 4);
-       HW_REG32(uBase, UART_FCON) |= (eTriggerLevel << 4);
+       modifyreg32(uBase + UART_FCON, 0x7 << 4, eTriggerLevel << 4);
 }
 
 /****************************************************************************
@@ -878,8 +872,7 @@ static void up_uart_set_rx_trigger_level(uint32_t uBase, UART_TRIGGER_LEVEL eTri
  ****************************************************************************/
 static void up_uart_set_rts_trigger_level(uint32_t uBase, UART_RTS_TRIGGER_LEVEL eRTSTriggerLevel)
 {
-       HW_REG32(uBase, UART_MCON) &= ~(0x7 << 5);
-       HW_REG32(uBase, UART_MCON) |= (eRTSTriggerLevel << 5);
+       modifyreg32(uBase + UART_MCON, 0x7 << 5, eRTSTriggerLevel << 5);
 }
 
 /****************************************************************************
@@ -897,8 +890,7 @@ static void up_uart_set_rts_trigger_level(uint32_t uBase, UART_RTS_TRIGGER_LEVEL
  ****************************************************************************/
 static void up_uart_set_tx_dma_burst_size(uint32_t uBase, UART_BURST_LENGTH eBurstLength)
 {
-       HW_REG32(uBase, UART_CON) &= ~(0x7 << 20);
-       HW_REG32(uBase, UART_CON) |= (eBurstLength << 20);
+       modifyreg32(uBase + UART_CON, 0x7 << 20, eBurstLength << 20);
 }
 
 /****************************************************************************
@@ -916,8 +908,7 @@ static void up_uart_set_tx_dma_burst_size(uint32_t uBase, UART_BURST_LENGTH eBur
  ****************************************************************************/
 static void up_uart_set_rx_dma_burst_size(uint32_t uBase, UART_BURST_LENGTH eBurstLength)
 {
-       HW_REG32(uBase, UART_CON) &= ~(0x7 << 16);
-       HW_REG32(uBase, UART_CON) |= (eBurstLength << 16);
+       modifyreg32(uBase + UART_CON, 0x7 << 16, eBurstLength << 16);
 }
 
 /****************************************************************************
@@ -935,7 +926,7 @@ static void up_uart_set_rx_dma_burst_size(uint32_t uBase, UART_BURST_LENGTH eBur
  ****************************************************************************/
 static void up_uart_clear_interrupt_status(uint32_t uBase, UART_INTERRUPT eInt)
 {
-       HW_REG32(uBase, UART_INTP) |= eInt;
+       putreg32(eInt, uBase + UART_INTP);
 }
 
 /****************************************************************************
@@ -964,14 +955,14 @@ static inline void up_disableuartint(struct up_dev_s *priv, uint32_t *im)
 
        priv->im = ALL_INT;
 
-       HW_REG32(priv->uartbase, UART_INTM) = priv->im;
+       putreg32(priv->im, priv->uartbase + UART_INTM);
 
        if (priv->im & ERROR_INT) {
-               HW_REG32(priv->uartbase, UART_CON) &= ~(0x1 << 6);
+               modifyreg32(priv->uartbase + UART_CON, 0x1 << 6, 0);
        }
 
        if (priv->im & MODEM_INT) {
-               HW_REG32(priv->uartbase, UART_MCON) &= ~(0x1 << 3);
+               modifyreg32(priv->uartbase + UART_MCON, 0x1 << 3, 0);
        }
 }
 
@@ -994,14 +985,14 @@ static inline void up_restoreuartint(struct up_dev_s *priv, uint32_t im)
        priv->im = im;
 
        if (priv->im & ERROR_INT) {
-               HW_REG32(priv->uartbase, UART_CON) |= (0x1 << 6);
+               modifyreg32(priv->uartbase + UART_CON, 0, 0x1 << 6);
        }
 
        if (priv->im & MODEM_INT) {
-               HW_REG32(priv->uartbase, UART_MCON) |= (0x1 << 3);
+               modifyreg32(priv->uartbase + UART_MCON, 0, 0x1 << 3);
        }
 
-       HW_REG32(priv->uartbase, UART_INTM) = priv->im;
+       putreg32(priv->im, priv->uartbase + UART_INTM);
 }
 
 /****************************************************************************
@@ -1075,7 +1066,7 @@ static int up_setup(struct uart_dev_s *dev)
 
        uart_init(priv->eCh);
 
-       priv->im = HW_REG32(priv->uartbase, UART_INTM);
+       priv->im = getreg32(priv->uartbase + UART_INTM);
        return OK;
 }
 
@@ -1206,8 +1197,8 @@ static int up_interrupt(int irq, void *context, void *arg)
 
                /* Get the masked UART status and clear the pending interrupts. */
 
-               mis = (HW_REG32(priv->uartbase, UART_INTP) & UART_INTP_MASK);
-               HW_REG32(priv->uartbase, UART_INTP) = mis;
+               mis = getreg32(priv->uartbase + UART_INTP) & UART_INTP_MASK;
+               putreg32(mis, priv->uartbase + UART_INTP);
 
                /* Handle incoming, receive bytes (with or without timeout) */
 
@@ -1331,9 +1322,10 @@ static int up_receive(struct uart_dev_s *dev, uint32_t *status)
        *status = 0;
        int empty;
        do {
-               empty = !(__raw_readl(priv->uartbase + UART_FSTAT) & UART_FSTAT_RX_MASK);
+               empty = !(getreg32(priv->uartbase + UART_FSTAT) & UART_FSTAT_RX_MASK);
        } while (empty);
-       return (HW_REG32(priv->uartbase, UART_RXH) & UART_RX_MASK);
+
+       return getreg32(priv->uartbase + UART_RXH) & UART_RX_MASK;
 }
 
 /****************************************************************************
@@ -1379,7 +1371,7 @@ static bool up_rxavailable(struct uart_dev_s *dev)
 {
        struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
 
-       return ((HW_REG32(priv->uartbase, UART_FSTAT) & UART_FSTAT_RX_MASK) != 0);
+       return ((getreg32(priv->uartbase + UART_FSTAT) & UART_FSTAT_RX_MASK) != 0);
 }
 
 /****************************************************************************
@@ -1398,8 +1390,7 @@ static bool up_rxavailable(struct uart_dev_s *dev)
 static void up_send(struct uart_dev_s *dev, int ch)
 {
        struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
-       HW_REG32(priv->uartbase, UART_TXH) = ch;
-
+       putreg32(ch, priv->uartbase + UART_TXH);
 }
 
 /****************************************************************************
@@ -1463,7 +1454,7 @@ static void up_txint(struct uart_dev_s *dev, bool enable)
 static bool up_txready(struct uart_dev_s *dev)
 {
        struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
-       return ((HW_REG32(priv->uartbase, UART_FSTAT) & UART_FSTAT_TX_MASK) == 0);
+       return ((getreg32(priv->uartbase + UART_FSTAT) & UART_FSTAT_TX_MASK) == 0);
 
 }
 
@@ -1482,7 +1473,7 @@ static bool up_txready(struct uart_dev_s *dev)
 static bool up_txempty(struct uart_dev_s *dev)
 {
        struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
-       return ((HW_REG32(priv->uartbase, UART_FSTAT) & UART_FSTAT_TX_MASK) == 0);
+       return ((getreg32(priv->uartbase + UART_FSTAT) & UART_FSTAT_TX_MASK) == 0);
 }
 
 /****************************************************************************
@@ -1504,7 +1495,7 @@ static void uart_send_data(UART_CHANNEL eCh, char cData)
        struct up_dev_s *priv;
        priv = g_uart_port[CONSOLE_PORT].priv;
        while (!up_txempty(&g_uart_port[CONSOLE_PORT])) ;
-       HW_REG32(priv->uartbase, UART_TXH) = cData;
+       putreg32(cData, priv->uartbase + UART_TXH);
 }
 
 /****************************************************************************

diff --git a/os/arch/arm/src/s5j/s5j_spi.c b/os/arch/arm/src/s5j/s5j_spi.c
index bd910c4..65dc59a 100644 (file)
--- a/os/arch/arm/src/s5j/s5j_spi.c
+++ b/os/arch/arm/src/s5j/s5j_spi.c
@@ -394,14 +394,14 @@ static void spi_select(struct spi_dev_s *dev, enum spi_dev_e devid, bool selecte
        pSPIRegs = (SPI_SFR *) priv->base;
        unsigned int cs_reg;
 
-       cs_reg = Inp32(&pSPIRegs->CS_REG);
+       cs_reg = getreg32(&pSPIRegs->CS_REG);
        cs_reg |= CS_REG_nSS_INACTIVE;
 
        if (selected == TRUE) {
                cs_reg &= ~CS_REG_nSS_INACTIVE;
        }
 
-       Outp32(&pSPIRegs->CS_REG, cs_reg);
+       putreg32(cs_reg, &pSPIRegs->CS_REG);
 }
 
 /****************************************************************************
@@ -417,13 +417,13 @@ void spi_set_initial(struct spi_dev_s *dev)
        SPI_SFR *pSPIRegs;
        pSPIRegs = (SPI_SFR *) priv->base;
 
-       Outp32(&pSPIRegs->CH_CFG, CH_CFG_HIGH_SPEED_DIS | CH_CFG_FIFO_FLUSH_OFF | CH_CFG_MASTER | CH_CFG_MODE(SPIDEV_MODE0) | CH_CFG_RX_CH_ON | CH_CFG_TX_CH_ON);       /* TX/RX enable. Master.CPHA 00. */
+       putreg32(CH_CFG_HIGH_SPEED_DIS | CH_CFG_FIFO_FLUSH_OFF | CH_CFG_MASTER | CH_CFG_MODE(SPIDEV_MODE0) | CH_CFG_RX_CH_ON | CH_CFG_TX_CH_ON, &pSPIRegs->CH_CFG);     /* TX/RX enable. Master.CPHA 00. */
 
-       Outp32(&pSPIRegs->MODE_CFG, MODE_CFG_CH_WIDTH_8 | MODE_CFG_TRLNG_CNT(0) | MODE_CFG_BUS_WIDTH_8 | MODE_CFG_RX_RDY_LVL(0) | MODE_CFG_TX_RDY_LVL(0) | MODE_CFG_DMA_RX_OFF | MODE_CFG_DMA_TX_OFF | MODE_CFG_DMA_SINGLE);    /*  No FIFO. N0 DMA. 8 bits */
+       putreg32(MODE_CFG_CH_WIDTH_8 | MODE_CFG_TRLNG_CNT(0) | MODE_CFG_BUS_WIDTH_8 | MODE_CFG_RX_RDY_LVL(0) | MODE_CFG_TX_RDY_LVL(0) | MODE_CFG_DMA_RX_OFF | MODE_CFG_DMA_TX_OFF | MODE_CFG_DMA_SINGLE, &pSPIRegs->MODE_CFG);  /*  No FIFO. N0 DMA. 8 bits */
 
-       Outp32(&pSPIRegs->CS_REG, CS_REG_nSS_TIME_CNT(0) | CS_REG_nSS_MANUAL | CS_REG_nSS_INACTIVE);    /* CS Manual Passive */
+       putreg32(CS_REG_nSS_TIME_CNT(0) | CS_REG_nSS_MANUAL | CS_REG_nSS_INACTIVE, &pSPIRegs->CS_REG);  /* CS Manual Passive */
 
-       Outp32(&pSPIRegs->SPI_INT_EN, 0);       /* Disable Interrupts */
+       putreg32(0, &pSPIRegs->SPI_INT_EN);     /* Disable Interrupts */
 }
 
 /*****************************************************************************
@@ -440,9 +440,9 @@ static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode)
        pSPIRegs = (SPI_SFR *) priv->base;
        unsigned int ch_cfg;
 
-       ch_cfg = Inp32(&pSPIRegs->CH_CFG);
+       ch_cfg = getreg32(&pSPIRegs->CH_CFG);
        ch_cfg = (ch_cfg & CH_CFG_MODE_MASK) | CH_CFG_MODE(mode);
-       Outp32(&pSPIRegs->CH_CFG, ch_cfg);
+       putreg32(ch_cfg, &pSPIRegs->CH_CFG);
 }
 
 /*****************************************************************************
@@ -456,9 +456,9 @@ inline void spi_fifo_flush(SPI_SFR *pSPIRegs)
 {
        unsigned int ch_cfg;
 
-       ch_cfg = Inp32(&pSPIRegs->CH_CFG);
-       Outp32(&pSPIRegs->CH_CFG, CH_CFG_FIFO_FLUSH);
-       Outp32(&pSPIRegs->CH_CFG, ch_cfg);
+       ch_cfg = getreg32(&pSPIRegs->CH_CFG);
+       putreg32(CH_CFG_FIFO_FLUSH, &pSPIRegs->CH_CFG);
+       putreg32(ch_cfg, &pSPIRegs->CH_CFG);
 }
 
 /****************************************************************************
@@ -475,7 +475,7 @@ static void spi_setbits(struct spi_dev_s *dev, int nbits)
        pSPIRegs = (SPI_SFR *) priv->base;
        unsigned int mode_cfg;
 
-       mode_cfg = Inp32(&pSPIRegs->MODE_CFG);
+       mode_cfg = getreg32(&pSPIRegs->MODE_CFG);
        mode_cfg = mode_cfg & (~(MODE_CFG_BUS_WDT_MASK | MODE_CFG_CH_WDT_MASK));
 
        switch (nbits) {
@@ -499,7 +499,7 @@ static void spi_setbits(struct spi_dev_s *dev, int nbits)
                DEBUGASSERT(0 == 1);
        }
 
-       Outp32(&pSPIRegs->MODE_CFG, mode_cfg);
+       putreg32(mode_cfg, &pSPIRegs->MODE_CFG);
 }
 
 /****************************************************************************
@@ -556,13 +556,13 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbu
        if ((rxbuffer == NULL) && (txbuffer == NULL)) {
                while (received < nwords) {
                        if (sent < nwords)
-                               if (SPI_STAT_TX_FIFO_LVL(Inp32(&pSPIRegs->SPI_STATUS)) < 64) {
-                                       Outp32(&pSPIRegs->SPI_TX_DATA, 0);
+                               if (SPI_STAT_TX_FIFO_LVL(getreg32(&pSPIRegs->SPI_STATUS)) < 64) {
+                                       putreg32(0, &pSPIRegs->SPI_TX_DATA);
                                        sent++;
                                }
 
-                       if (SPI_STAT_RX_FIFO_LVL(Inp32(&pSPIRegs->SPI_STATUS)) > 0) {
-                               dummy_rx = Inp32(&pSPIRegs->SPI_RX_DATA);
+                       if (SPI_STAT_RX_FIFO_LVL(getreg32(&pSPIRegs->SPI_STATUS)) > 0) {
+                               dummy_rx = getreg32(&pSPIRegs->SPI_RX_DATA);
                                received++;
                        }
                }
@@ -572,12 +572,12 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbu
        if (rxbuffer == NULL) {
                while (received < nwords) {
                        if (sent < nwords)
-                               if (SPI_STAT_TX_FIFO_LVL(Inp32(&pSPIRegs->SPI_STATUS)) < 64) {
-                                       Outp32(&pSPIRegs->SPI_TX_DATA, ((unsigned char *)txbuffer)[sent++]);
+                               if (SPI_STAT_TX_FIFO_LVL(getreg32(&pSPIRegs->SPI_STATUS)) < 64) {
+                                       putreg32(((unsigned char *)txbuffer)[sent++], &pSPIRegs->SPI_TX_DATA);
                                }
 
-                       if (SPI_STAT_RX_FIFO_LVL(Inp32(&pSPIRegs->SPI_STATUS)) > 0) {
-                               dummy_rx = Inp32(&pSPIRegs->SPI_RX_DATA);
+                       if (SPI_STAT_RX_FIFO_LVL(getreg32(&pSPIRegs->SPI_STATUS)) > 0) {
+                               dummy_rx = getreg32(&pSPIRegs->SPI_RX_DATA);
                                received++;
                        }
                }
@@ -587,12 +587,12 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbu
        if (txbuffer == NULL) {
                while (received < nwords) {
                        if (sent < nwords)
-                               if (SPI_STAT_TX_FIFO_LVL(Inp32(&pSPIRegs->SPI_STATUS)) < 64) {
-                                       Outp32(&pSPIRegs->SPI_TX_DATA, ((unsigned char *)rxbuffer)[sent++]);
+                               if (SPI_STAT_TX_FIFO_LVL(getreg32(&pSPIRegs->SPI_STATUS)) < 64) {
+                                       putreg32(((unsigned char *)rxbuffer)[sent++], &pSPIRegs->SPI_TX_DATA);
                                }
 
-                       if (SPI_STAT_RX_FIFO_LVL(Inp32(&pSPIRegs->SPI_STATUS)) > 0) {
-                               ((unsigned char *)rxbuffer)[received++] = Inp32(&pSPIRegs->SPI_RX_DATA);
+                       if (SPI_STAT_RX_FIFO_LVL(getreg32(&pSPIRegs->SPI_STATUS)) > 0) {
+                               ((unsigned char *)rxbuffer)[received++] = getreg32(&pSPIRegs->SPI_RX_DATA);
                        }
 
                }
@@ -601,12 +601,12 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbu
 
        while (received < nwords) {
                if (sent < nwords)
-                       if (SPI_STAT_TX_FIFO_LVL(Inp32(&pSPIRegs->SPI_STATUS)) < 64) {
-                               Outp32(&pSPIRegs->SPI_TX_DATA, ((unsigned char *)txbuffer)[sent++]);
+                       if (SPI_STAT_TX_FIFO_LVL(getreg32(&pSPIRegs->SPI_STATUS)) < 64) {
+                               putreg32(((unsigned char *)txbuffer)[sent++], &pSPIRegs->SPI_TX_DATA);
                        }
 
-               if (SPI_STAT_RX_FIFO_LVL(Inp32(&pSPIRegs->SPI_STATUS)) > 0) {
-                       ((unsigned char *)rxbuffer)[received++] = Inp32(&pSPIRegs->SPI_RX_DATA);
+               if (SPI_STAT_RX_FIFO_LVL(getreg32(&pSPIRegs->SPI_STATUS)) > 0) {
+                       ((unsigned char *)rxbuffer)[received++] = getreg32(&pSPIRegs->SPI_RX_DATA);
                }
 
        }