drm/i915/ddi: Don't frob the DP link scramble disabling flag

According to BSpec this flag should not be changed while the DDI
function is enabled. On BDW+ the DP_TP_CTL register spec also states it
explicitly that the HW takes care of enabling/disabling the scrambling
for training patterns (and it must stay enabled for normal pixel
output). Assume that this HW automatic handling of scrambling is also
true for HSW.

BSpec: 8013, 7557, 50484

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200714153141.10280-1-imre.deak@intel.com
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 2c484b55bcdf7a333fa406be658f6c00221d7e69..c467f18d5e1bec36f3edcbf68102df5e3ffb6c8a 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4037,8 +4037,7 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
                        intel_wait_ddi_buf_idle(dev_priv, port);
        }
 
-       dp_tp_ctl = DP_TP_CTL_ENABLE |
-                   DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
+       dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1;
        if (intel_dp->link_mst)
                dp_tp_ctl |= DP_TP_CTL_MODE_MST;
        else {
@@ -4066,11 +4065,6 @@ static void intel_ddi_set_link_train(struct intel_dp *intel_dp,
 
        temp = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
 
-       if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
-               temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
-       else
-               temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
-
        temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
        switch (dp_train_pat & train_pat_mask) {
        case DP_TRAINING_PATTERN_DISABLE: