imx8ulp: soc: Check the DBD_EN fuse before setting RDC

S400 enables RDC only when the DBD_EN is fused. Otherwise, the RDC
is allowed by all masters.

Current S400 has issue if the XRDC has released to A35, then A35 reset
will fail in ROM due to S400 fails to get XRDC.
So temp work around is checking the DBD_EN, if it is not fused, we
don't need to call release XRDC or TRDC.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>

diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index bba6323..b25f5f2 100644 (file)
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -23,6 +23,7 @@
 #include <dm/uclass.h>
 #include <dm/device.h>
 #include <dm/uclass-internal.h>
+#include <fuse.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -468,11 +469,22 @@ static int trdc_set_access(void)
 int arch_cpu_init(void)
 {
        if (IS_ENABLED(CONFIG_SPL_BUILD)) {
+               u32 val = 0;
+               int ret;
+               bool rdc_en = true; /* Default assume DBD_EN is set */
+
                /* Disable wdog */
                init_wdog();
 
+               /* Read DBD_EN fuse */
+               ret = fuse_read(8, 1, &val);
+               if (!ret)
+                       rdc_en = !!(val & 0x4000);
+
                if (get_boot_mode() == SINGLE_BOOT) {
-                       release_rdc(RDC_TRDC);
+                       if (rdc_en)
+                               release_rdc(RDC_TRDC);
+
                        trdc_set_access();
                        /* LPAV to APD */
                        setbits_le32(0x2802B044, BIT(7));
@@ -482,8 +494,10 @@ int arch_cpu_init(void)
                        setbits_le32(0x2802B04C, BIT(1) | BIT(2) | BIT(3) | BIT(4));
                }
 
-               /* release xrdc, then allow A35 to write SRAM2 */
-               release_rdc(RDC_XRDC);
+               /* Release xrdc, then allow A35 to write SRAM2 */
+               if (rdc_en)
+                       release_rdc(RDC_XRDC);
+
                xrdc_mrc_region_set_access(2, CONFIG_SPL_TEXT_BASE, 0xE00);
 
                clock_init();