PR target/56788

	* config/i386/i386.c (bdesc_multi_arg) <IX86_BUILTIN_VFRCZSS>:
	Declare as MULTI_ARG_1_SF instruction.
	<IX86_BUILTIN_VFRCZSD>: Decleare as MULTI_ARG_1_DF instruction.
	* config/i386/sse.md (*xop_vmfrcz<mode>2): Rename
	from *xop_vmfrcz_<mode>.
	* config/i386/xopintrin.h (_mm_frcz_ss): Use __builtin_ia32_movss
	to merge scalar result with __A.
	(_mm_frcz_sd): Use __builtin_ia32_movsd to merge scalar
	result with __A.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@205306 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 32955d7..331cbbb 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,16 @@
+2013-11-23  Uros Bizjak  <ubizjak@gmail.com>
+
+       PR target/56788
+       * config/i386/i386.c (bdesc_multi_arg) <IX86_BUILTIN_VFRCZSS>:
+       Declare as MULTI_ARG_1_SF instruction.
+       <IX86_BUILTIN_VFRCZSD>: Decleare as MULTI_ARG_1_DF instruction.
+       * config/i386/sse.md (*xop_vmfrcz<mode>2): Rename
+       from *xop_vmfrcz_<mode>.
+       * config/i386/xopintrin.h (_mm_frcz_ss): Use __builtin_ia32_movss
+       to merge scalar result with __A.
+       (_mm_frcz_sd): Use __builtin_ia32_movsd to merge scalar
+       result with __A.
+
 2013-11-23  Eric Botcazou  <ebotcazou@adacore.com>
 
        * gimplify.h (recalculate_side_effects): Delete.
@@ -87,16 +100,14 @@
        (get_adjustment_for_base): Use operator enum.
        (sra_ipa_modify_expr): Rename to ipa_modify_expr and move to
        ipa-prop.c.
-       (sra_ipa_modify_assign): Rename sra_ipa_modify_expr to
-       ipa_modify_expr.
+       (sra_ipa_modify_assign): Rename sra_ipa_modify_expr to ipa_modify_expr.
        (ipa_sra_modify_function_body): Same.  No longer static.
        (sra_ipa_reset_debug_stmts): Use operator enum.
        (modify_function): Do not pass prefix argument.
 
 2013-11-22  Jakub Jelinek  <jakub@redhat.com>
 
-       * ubsan.c (ubsan_source_location): Don't crash on
-       unknown locations.
+       * ubsan.c (ubsan_source_location): Don't crash on unknown locations.
        (ubsan_pass): Ignore clobber stmts.
 
        * sanitizer.def (BUILT_IN_UBSAN_HANDLE_MISSING_RETURN): New built-in.
@@ -136,8 +147,7 @@
        (cond_arg_set_in_b): Remove.
        (record_temporary_equivalences_from_stmts_at_dest): New bitmap
        arguments and a boolean indicating if we have passed a backedge.
-       If we have passed a backedge, then perform invalidations as
-       needed.
+       If we have passed a backedge, then perform invalidations as needed.
        (thread_around_empty_blocks): If we have seen a backedge, then
        use the dummy simplify routine.
        (thread_through_normal_block): Likewise.  Pass bitmaps and
@@ -418,7 +428,8 @@
 2013-11-22  Tejas Belagod  <tejas.belagod@arm.com>
 
        * config/aarch64/aarch64-simd.md (vec_pack_trunc_<mode>,
-       vec_pack_trunc_v2df, vec_pack_trunc_df): Swap source ops for big-endian.
+       vec_pack_trunc_v2df, vec_pack_trunc_df): Swap source ops for
+       big-endian.
 
 2013-11-22  Tejas Belagod  <tejas.belagod@arm.com>
 

diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 3c516f4..23d833e 100644 (file)
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -29189,8 +29189,8 @@ static const struct builtin_description bdesc_multi_arg[] =
   { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv8hi3,         "__builtin_ia32_vpshlw",      IX86_BUILTIN_VPSHLW,      UNKNOWN,      (int)MULTI_ARG_2_HI },
   { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv16qi3,        "__builtin_ia32_vpshlb",      IX86_BUILTIN_VPSHLB,      UNKNOWN,      (int)MULTI_ARG_2_QI },
 
-  { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2,       "__builtin_ia32_vfrczss",     IX86_BUILTIN_VFRCZSS,     UNKNOWN,      (int)MULTI_ARG_2_SF },
-  { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2,       "__builtin_ia32_vfrczsd",     IX86_BUILTIN_VFRCZSD,     UNKNOWN,      (int)MULTI_ARG_2_DF },
+  { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2,       "__builtin_ia32_vfrczss",     IX86_BUILTIN_VFRCZSS,     UNKNOWN,      (int)MULTI_ARG_1_SF },
+  { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2,       "__builtin_ia32_vfrczsd",     IX86_BUILTIN_VFRCZSD,     UNKNOWN,      (int)MULTI_ARG_1_DF },
   { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4sf2,         "__builtin_ia32_vfrczps",     IX86_BUILTIN_VFRCZPS,     UNKNOWN,      (int)MULTI_ARG_1_SF },
   { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv2df2,         "__builtin_ia32_vfrczpd",     IX86_BUILTIN_VFRCZPD,     UNKNOWN,      (int)MULTI_ARG_1_DF },
   { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv8sf2,         "__builtin_ia32_vfrczps256",  IX86_BUILTIN_VFRCZPS256,  UNKNOWN,      (int)MULTI_ARG_1_SF2 },

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 6d6e16e..7a47f27 100644 (file)
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -13193,7 +13193,6 @@
   [(set_attr "type" "ssecvt1")
    (set_attr "mode" "<MODE>")])
 
-;; scalar insns
 (define_expand "xop_vmfrcz<mode>2"
   [(set (match_operand:VF_128 0 "register_operand")
        (vec_merge:VF_128
@@ -13203,11 +13202,9 @@
          (match_dup 3)
          (const_int 1)))]
   "TARGET_XOP"
-{
-  operands[3] = CONST0_RTX (<MODE>mode);
-})
+  "operands[3] = CONST0_RTX (<MODE>mode);")
 
-(define_insn "*xop_vmfrcz_<mode>"
+(define_insn "*xop_vmfrcz<mode>2"
   [(set (match_operand:VF_128 0 "register_operand" "=x")
        (vec_merge:VF_128
          (unspec:VF_128

diff --git a/gcc/config/i386/xopintrin.h b/gcc/config/i386/xopintrin.h
index e0d148a..49cea8e 100644 (file)
--- a/gcc/config/i386/xopintrin.h
+++ b/gcc/config/i386/xopintrin.h
@@ -747,13 +747,17 @@ _mm_frcz_pd (__m128d __A)
 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
 _mm_frcz_ss (__m128 __A, __m128 __B)
 {
-  return (__m128) __builtin_ia32_vfrczss ((__v4sf)__A, (__v4sf)__B);
+  return (__m128) __builtin_ia32_movss ((__v4sf)__A,
+                                       (__v4sf)
+                                       __builtin_ia32_vfrczss ((__v4sf)__B));
 }
 
 extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
 _mm_frcz_sd (__m128d __A, __m128d __B)
 {
-  return (__m128d) __builtin_ia32_vfrczsd ((__v2df)__A, (__v2df)__B);
+  return (__m128d) __builtin_ia32_movsd ((__v2df)__A,
+                                        (__v2df)
+                                        __builtin_ia32_vfrczsd ((__v2df)__B));
 }
 
 extern __inline __m256 __attribute__((__gnu_inline__, __always_inline__, __artificial__))