vpu: add support for tl1 [1/1]

PD#172587

Problem:
Bringup vpu for TL1.

Solution:
Add vpu support for TL1.

Verify:
Verified on PTM/PXP.

Change-Id: Ic2fb7682ddc1b21840e1be1d8462d4c0902e739d
Signed-off-by: Evoke Zhang <evoke.zhang@amlogic.com>

diff --git a/drivers/amlogic/media/common/vpu/vpu.c b/drivers/amlogic/media/common/vpu/vpu.c
index 2a10da6..d7f3cff 100644 (file)
--- a/drivers/amlogic/media/common/vpu/vpu.c
+++ b/drivers/amlogic/media/common/vpu/vpu.c
@@ -38,7 +38,8 @@
 /* v03: add txlx support */
 /* v04: add g12a support */
 /* v05: add txl support */
-#define VPU_VERION        "v05"
+/* v20180925: add tl1 support */
+#define VPU_VERION        "v20180925"
 
 int vpu_debug_print_flag;
 static spinlock_t vpu_mem_lock;
@@ -489,7 +490,7 @@ void switch_vpu_mem_pd_vmod(unsigned int vmod, int flag)
        unsigned long flags = 0;
        unsigned int _val, _reg, _bit, _len;
        struct vpu_ctrl_s *table;
-       int i = 0, ret = 0, cnt;
+       int i = 0, ret = 0, done = 0, cnt;
 
        ret = vpu_chip_valid_check();
        if (ret)
@@ -504,23 +505,29 @@ void switch_vpu_mem_pd_vmod(unsigned int vmod, int flag)
        cnt = vpu_conf.data->mem_pd_table_cnt;
        table = vpu_conf.data->mem_pd_table;
        while (i < cnt) {
-               if (table[i].vmod == vmod)
-                       break;
                if (table[i].vmod == VPU_MOD_MAX)
                        break;
+               if (table[i].vmod == vmod) {
+                       _reg = table[i].reg;
+                       _bit = table[i].bit;
+                       _len = table[i].len;
+                       if (flag == VPU_MEM_POWER_ON) {
+                               _val = 0x0;
+                       } else {
+                               if (_len == 32)
+                                       _val = 0xffffffff;
+                               else
+                                       _val = (1 << _len) - 1;
+                       }
+                       vpu_hiu_setb(_reg, _val, _bit, _len);
+                       done++;
+               }
                i++;
        }
-       if (table[i].vmod < VPU_MOD_MAX) {
-               _val = (flag == VPU_MEM_POWER_ON) ? 0x0 : 0x3;
-               _reg = table[i].reg;
-               _bit = table[i].bit;
-               _len = table[i].len;
-               vpu_hiu_setb(_reg, _val, _bit, _len);
-       }
 
        spin_unlock_irqrestore(&vpu_mem_lock, flags);
 
-       if (table[i].vmod == VPU_MOD_MAX)
+       if (done == 0)
                VPUPR("switch_vpu_mem_pd: unsupport vpu mod: %d\n", vmod);
        if (vpu_debug_print_flag) {
                if (vmod < VPU_MOD_MAX) {
@@ -548,13 +555,11 @@ void switch_vpu_mem_pd_vmod(unsigned int vmod, int flag)
  *      ret = get_vpu_mem_pd_vmod(VPU_VIU_OSD1);
  *
  */
-#define VPU_MEM_PD_ERR        0xffff
-
 int get_vpu_mem_pd_vmod(unsigned int vmod)
 {
        unsigned int _reg, _bit, _len;
        struct vpu_ctrl_s *table;
-       int i = 0, ret = 0, cnt;
+       int i = 0, ret = 0, done = 0, cnt;
 
        ret = vpu_chip_valid_check();
        if (ret)
@@ -566,29 +571,28 @@ int get_vpu_mem_pd_vmod(unsigned int vmod)
 
        cnt = vpu_conf.data->mem_pd_table_cnt;
        table = vpu_conf.data->mem_pd_table;
+       ret = 0;
        while (i < cnt) {
-               if (table[i].vmod == vmod)
-                       break;
                if (table[i].vmod == VPU_MOD_MAX)
                        break;
+               if (table[i].vmod == vmod) {
+                       _reg = table[i].reg;
+                       _bit = table[i].bit;
+                       _len = table[i].len;
+                       ret += vpu_hiu_getb(_reg, _bit, _len);
+                       done++;
+               }
                i++;
        }
-       if (table[i].vmod == VPU_MOD_MAX) {
+       if (done == 0) {
                VPUPR("get_vpu_mem_pd: unsupport vpu mod: %d\n", vmod);
                return -1;
        }
 
-       _reg = table[i].reg;
-       _bit = table[i].bit;
-       _len = table[i].len;
-       ret = vpu_hiu_getb(_reg, _bit, _len);
-
        if (ret == 0)
                return VPU_MEM_POWER_ON;
-       else if ((ret == 0x3) || (ret == 0xf))
-               return VPU_MEM_POWER_DOWN;
        else
-               return -1;
+               return VPU_MEM_POWER_DOWN;
 }
 
 /* *********************************************** */
@@ -614,7 +618,7 @@ void switch_vpu_clk_gate_vmod(unsigned int vmod, int flag)
 {
        unsigned int _val, _reg, _bit, _len;
        struct vpu_ctrl_s *table;
-       int i = 0, ret = 0, m = 0, cnt;
+       int i = 0, ret = 0, done = 0, cnt;
        unsigned long flags = 0;
 
        ret = vpu_chip_valid_check();
@@ -630,26 +634,30 @@ void switch_vpu_clk_gate_vmod(unsigned int vmod, int flag)
        cnt = vpu_conf.data->clk_gate_table_cnt;
        table = vpu_conf.data->clk_gate_table;
        while (i < cnt) {
+               if (table[i].vmod == VPU_MAX)
+                       break;
                if (table[i].vmod == vmod) {
                        _reg = table[i].reg;
                        _bit = table[i].bit;
                        _len = table[i].len;
-                       if (flag == VPU_CLK_GATE_ON)
-                               _val = (1 << _len) - 1;
-                       else
+                       if (flag == VPU_CLK_GATE_ON) {
+                               if (_len == 32)
+                                       _val = 0xffffffff;
+                               else
+                                       _val = (1 << _len) - 1;
+                       } else {
                                _val = 0;
+                       }
                        vpu_vcbus_setb(_reg, _val, _bit, _len);
-                       m++;
-               } else if (table[i].vmod == VPU_MAX)
-                       break;
+                       done++;
+               }
                i++;
        }
 
        spin_unlock_irqrestore(&vpu_clk_gate_lock, flags);
 
-       if (m == 0)
+       if (done == 0)
                VPUPR("switch_vpu_clk_gate: unsupport vpu mod: %d\n", vmod);
-
        if (vpu_debug_print_flag) {
                if (vmod < VPU_MAX) {
                        VPUPR("switch_vpu_clk_gate: %s %s\n",
@@ -774,13 +782,15 @@ static ssize_t vpu_clk_debug(struct class *class, struct class_attribute *attr,
 static ssize_t vpu_mem_debug(struct class *class, struct class_attribute *attr,
                                const char *buf, size_t count)
 {
-       unsigned int tmp[2];
-       unsigned int _reg0, _reg1, _reg2;
+       unsigned int tmp[2], val;
+       unsigned int _reg0, _reg1, _reg2, _reg3, _reg4;
        int ret = 0, i;
 
        _reg0 = HHI_VPU_MEM_PD_REG0;
        _reg1 = HHI_VPU_MEM_PD_REG1;
        _reg2 = HHI_VPU_MEM_PD_REG2;
+       _reg3 = HHI_VPU_MEM_PD_REG3;
+       _reg4 = HHI_VPU_MEM_PD_REG4;
        switch (buf[0]) {
        case 'r':
                VPUPR("mem_pd0: 0x%08x\n", vpu_hiu_read(_reg0));
@@ -788,6 +798,10 @@ static ssize_t vpu_mem_debug(struct class *class, struct class_attribute *attr,
                        VPUPR("mem_pd1: 0x%08x\n", vpu_hiu_read(_reg1));
                if (vpu_conf.data->mem_pd_reg2_valid)
                        VPUPR("mem_pd2: 0x%08x\n", vpu_hiu_read(_reg2));
+               if (vpu_conf.data->mem_pd_reg3_valid)
+                       VPUPR("mem_pd2: 0x%08x\n", vpu_hiu_read(_reg3));
+               if (vpu_conf.data->mem_pd_reg4_valid)
+                       VPUPR("mem_pd2: 0x%08x\n", vpu_hiu_read(_reg4));
                break;
        case 'w':
                ret = sscanf(buf, "w %u %u", &tmp[0], &tmp[1]);
@@ -804,8 +818,13 @@ static ssize_t vpu_mem_debug(struct class *class, struct class_attribute *attr,
                break;
        case 'i':
                VPUPR("vpu modules:\n");
-               for (i = VPU_VIU_OSD1; i < VPU_MOD_MAX; i++)
-                       pr_info("    [%02d] %s\n", i, vpu_mod_table[i]);
+               for (i = VPU_VIU_OSD1; i < VPU_MOD_MAX; i++) {
+                       val = get_vpu_mem_pd_vmod(i);
+                       pr_info("  [%02d] %s    %s(%d)\n",
+                               i, vpu_mod_table[i],
+                               (val == VPU_MEM_POWER_ON) ? "ON" : "OFF",
+                               val);
+               }
                break;
        default:
                VPUERR("wrong mem_pd command\n");
@@ -961,6 +980,14 @@ static ssize_t vpu_debug_info(struct class *class,
                len += sprintf(buf+len, "  mem_pd2:      0x%08x\n",
                        vpu_hiu_read(HHI_VPU_MEM_PD_REG2));
        }
+       if (vpu_conf.data->mem_pd_reg3_valid) {
+               len += sprintf(buf+len, "  mem_pd3:      0x%08x\n",
+                       vpu_hiu_read(HHI_VPU_MEM_PD_REG3));
+       }
+       if (vpu_conf.data->mem_pd_reg4_valid) {
+               len += sprintf(buf+len, "  mem_pd4:      0x%08x\n",
+                       vpu_hiu_read(HHI_VPU_MEM_PD_REG4));
+       }
 
 #ifdef CONFIG_VPU_DYNAMIC_ADJ
        if (vpu_conf.clk_vmod) {
@@ -1161,13 +1188,11 @@ static int vpu_power_init_check(void)
        int ret = 0;
 
        val = vpu_hiu_getb(HHI_VPU_CLK_CNTL, 31, 1);
-       if (val) {
-               if (vpu_hiu_getb(HHI_VPU_CLK_CNTL, 24, 1) == 0)
-                       ret = 1;
-       } else {
-               if (vpu_hiu_getb(HHI_VPU_CLK_CNTL, 8, 1) == 0)
-                       ret = 1;
-       }
+       if (val)
+               val = vpu_hiu_getb(HHI_VPU_CLK_CNTL, 24, 1);
+       else
+               val = vpu_hiu_getb(HHI_VPU_CLK_CNTL, 8, 1);
+       ret = (val == 0) ? 1 : 0;
 
        return ret;
 }
@@ -1180,9 +1205,8 @@ static void vpu_power_init(void)
        if (ret)
                return;
 
-       vpu_conf.data->power_on();
+       vpu_power_on();
        vpu_mem_pd_init_off();
-       vpu_clk_gate_init_off();
        vpu_module_init_config();
 }
 
@@ -1196,6 +1220,8 @@ static struct vpu_data_s vpu_data_gxb = {
        .gp_pll_valid = 1,
        .mem_pd_reg1_valid = 1,
        .mem_pd_reg2_valid = 0,
+       .mem_pd_reg3_valid = 0,
+       .mem_pd_reg4_valid = 0,
 
        .mem_pd_table_cnt =
                sizeof(vpu_mem_pd_gxb) / sizeof(struct vpu_ctrl_s),
@@ -1204,12 +1230,13 @@ static struct vpu_data_s vpu_data_gxb = {
        .mem_pd_table = vpu_mem_pd_gxb,
        .clk_gate_table = vpu_clk_gate_gxb,
 
-       .power_on  = vpu_power_on_gx,
-       .power_off = vpu_power_off_gx,
+       .module_init_table_cnt = 0,
+       .module_init_table = NULL,
+       .reset_table = vpu_reset_gx,
 };
 
 static struct vpu_data_s vpu_data_gxtvbb = {
-       .chip_type = VPU_CHIP_GXBB,
+       .chip_type = VPU_CHIP_GXTVBB,
        .chip_name = "gxtvbb",
        .clk_level_dft = CLK_LEVEL_DFT_GXTVBB,
        .clk_level_max = CLK_LEVEL_MAX_GXTVBB,
@@ -1218,6 +1245,8 @@ static struct vpu_data_s vpu_data_gxtvbb = {
        .gp_pll_valid = 1,
        .mem_pd_reg1_valid = 1,
        .mem_pd_reg2_valid = 0,
+       .mem_pd_reg3_valid = 0,
+       .mem_pd_reg4_valid = 0,
 
        .mem_pd_table_cnt =
                sizeof(vpu_mem_pd_gxtvbb) / sizeof(struct vpu_ctrl_s),
@@ -1226,8 +1255,9 @@ static struct vpu_data_s vpu_data_gxtvbb = {
        .mem_pd_table = vpu_mem_pd_gxtvbb,
        .clk_gate_table = vpu_clk_gate_gxl,
 
-       .power_on  = vpu_power_on_gx,
-       .power_off = vpu_power_off_gx,
+       .module_init_table_cnt = 0,
+       .module_init_table = NULL,
+       .reset_table = vpu_reset_gx,
 };
 
 static struct vpu_data_s vpu_data_gxl = {
@@ -1240,6 +1270,8 @@ static struct vpu_data_s vpu_data_gxl = {
        .gp_pll_valid = 1,
        .mem_pd_reg1_valid = 1,
        .mem_pd_reg2_valid = 1,
+       .mem_pd_reg3_valid = 0,
+       .mem_pd_reg4_valid = 0,
 
        .mem_pd_table_cnt =
                sizeof(vpu_mem_pd_gxl) / sizeof(struct vpu_ctrl_s),
@@ -1248,8 +1280,9 @@ static struct vpu_data_s vpu_data_gxl = {
        .mem_pd_table = vpu_mem_pd_gxl,
        .clk_gate_table = vpu_clk_gate_gxl,
 
-       .power_on  = vpu_power_on_gx,
-       .power_off = vpu_power_off_gx,
+       .module_init_table_cnt = 0,
+       .module_init_table = NULL,
+       .reset_table = vpu_reset_gx,
 };
 
 static struct vpu_data_s vpu_data_gxm = {
@@ -1262,6 +1295,8 @@ static struct vpu_data_s vpu_data_gxm = {
        .gp_pll_valid = 1,
        .mem_pd_reg1_valid = 1,
        .mem_pd_reg2_valid = 1,
+       .mem_pd_reg3_valid = 0,
+       .mem_pd_reg4_valid = 0,
 
        .mem_pd_table_cnt =
                sizeof(vpu_mem_pd_gxl) / sizeof(struct vpu_ctrl_s),
@@ -1270,8 +1305,10 @@ static struct vpu_data_s vpu_data_gxm = {
        .mem_pd_table = vpu_mem_pd_gxl,
        .clk_gate_table = vpu_clk_gate_gxl,
 
-       .power_on  = vpu_power_on_gx,
-       .power_off = vpu_power_off_gx,
+       .module_init_table_cnt =
+               sizeof(vpu_module_init_gxm) / sizeof(struct vpu_ctrl_s),
+       .module_init_table = vpu_module_init_gxm,
+       .reset_table = vpu_reset_gx,
 };
 
 static struct vpu_data_s vpu_data_txl = {
@@ -1284,6 +1321,8 @@ static struct vpu_data_s vpu_data_txl = {
        .gp_pll_valid = 0,
        .mem_pd_reg1_valid = 1,
        .mem_pd_reg2_valid = 0,
+       .mem_pd_reg3_valid = 0,
+       .mem_pd_reg4_valid = 0,
 
        .mem_pd_table_cnt =
                sizeof(vpu_mem_pd_txl) / sizeof(struct vpu_ctrl_s),
@@ -1292,8 +1331,9 @@ static struct vpu_data_s vpu_data_txl = {
        .mem_pd_table = vpu_mem_pd_txl,
        .clk_gate_table = vpu_clk_gate_txl,
 
-       .power_on  = vpu_power_on_txlx,
-       .power_off = vpu_power_off_txlx,
+       .module_init_table_cnt = 0,
+       .module_init_table = NULL,
+       .reset_table = vpu_reset_gx,
 };
 
 static struct vpu_data_s vpu_data_txlx = {
@@ -1306,6 +1346,8 @@ static struct vpu_data_s vpu_data_txlx = {
        .gp_pll_valid = 1,
        .mem_pd_reg1_valid = 1,
        .mem_pd_reg2_valid = 1,
+       .mem_pd_reg3_valid = 0,
+       .mem_pd_reg4_valid = 0,
 
        .mem_pd_table_cnt =
                sizeof(vpu_mem_pd_txlx) / sizeof(struct vpu_ctrl_s),
@@ -1314,8 +1356,10 @@ static struct vpu_data_s vpu_data_txlx = {
        .mem_pd_table = vpu_mem_pd_txlx,
        .clk_gate_table = vpu_clk_gate_txlx,
 
-       .power_on  = vpu_power_on_txlx,
-       .power_off = vpu_power_off_txlx,
+       .module_init_table_cnt =
+               sizeof(vpu_module_init_txlx) / sizeof(struct vpu_ctrl_s),
+       .module_init_table = vpu_module_init_txlx,
+       .reset_table = vpu_reset_txlx,
 };
 
 static struct vpu_data_s vpu_data_axg = {
@@ -1328,6 +1372,8 @@ static struct vpu_data_s vpu_data_axg = {
        .gp_pll_valid = 0,
        .mem_pd_reg1_valid = 0,
        .mem_pd_reg2_valid = 0,
+       .mem_pd_reg3_valid = 0,
+       .mem_pd_reg4_valid = 0,
 
        .mem_pd_table_cnt =
                sizeof(vpu_mem_pd_axg) / sizeof(struct vpu_ctrl_s),
@@ -1336,8 +1382,9 @@ static struct vpu_data_s vpu_data_axg = {
        .mem_pd_table = vpu_mem_pd_axg,
        .clk_gate_table = vpu_clk_gate_axg,
 
-       .power_on  = vpu_power_on_txlx,
-       .power_off = vpu_power_off_txlx,
+       .module_init_table_cnt = 0,
+       .module_init_table = NULL,
+       .reset_table = vpu_reset_txlx,
 };
 
 static struct vpu_data_s vpu_data_g12a = {
@@ -1350,16 +1397,19 @@ static struct vpu_data_s vpu_data_g12a = {
        .gp_pll_valid = 0,
        .mem_pd_reg1_valid = 1,
        .mem_pd_reg2_valid = 1,
+       .mem_pd_reg3_valid = 0,
+       .mem_pd_reg4_valid = 0,
 
        .mem_pd_table_cnt =
-               sizeof(vpu_mem_pd_g12b) / sizeof(struct vpu_ctrl_s),
+               sizeof(vpu_mem_pd_g12a) / sizeof(struct vpu_ctrl_s),
        .clk_gate_table_cnt =
                sizeof(vpu_clk_gate_g12a) / sizeof(struct vpu_ctrl_s),
-       .mem_pd_table = vpu_mem_pd_g12b,
+       .mem_pd_table = vpu_mem_pd_g12a,
        .clk_gate_table = vpu_clk_gate_g12a,
 
-       .power_on  = vpu_power_on_txlx,
-       .power_off = vpu_power_off_txlx,
+       .module_init_table_cnt = 0,
+       .module_init_table = NULL,
+       .reset_table = vpu_reset_txlx,
 };
 
 static struct vpu_data_s vpu_data_g12b = {
@@ -1372,16 +1422,44 @@ static struct vpu_data_s vpu_data_g12b = {
        .gp_pll_valid = 0,
        .mem_pd_reg1_valid = 1,
        .mem_pd_reg2_valid = 1,
+       .mem_pd_reg3_valid = 0,
+       .mem_pd_reg4_valid = 0,
 
        .mem_pd_table_cnt =
-               sizeof(vpu_mem_pd_g12a) / sizeof(struct vpu_ctrl_s),
+               sizeof(vpu_mem_pd_g12b) / sizeof(struct vpu_ctrl_s),
        .clk_gate_table_cnt =
                sizeof(vpu_clk_gate_g12a) / sizeof(struct vpu_ctrl_s),
-       .mem_pd_table = vpu_mem_pd_g12a,
+       .mem_pd_table = vpu_mem_pd_g12b,
        .clk_gate_table = vpu_clk_gate_g12a,
 
-       .power_on  = vpu_power_on_txlx,
-       .power_off = vpu_power_off_txlx,
+       .module_init_table_cnt = 0,
+       .module_init_table = NULL,
+       .reset_table = vpu_reset_txlx,
+};
+
+static struct vpu_data_s vpu_data_tl1 = {
+       .chip_type = VPU_CHIP_TL1,
+       .chip_name = "tl1",
+       .clk_level_dft = CLK_LEVEL_DFT_G12A,
+       .clk_level_max = CLK_LEVEL_MAX_G12A,
+       .fclk_div_table = fclk_div_table_g12a,
+
+       .gp_pll_valid = 0,
+       .mem_pd_reg1_valid = 1,
+       .mem_pd_reg2_valid = 1,
+       .mem_pd_reg3_valid = 1,
+       .mem_pd_reg4_valid = 1,
+
+       .mem_pd_table_cnt =
+               sizeof(vpu_mem_pd_tl1) / sizeof(struct vpu_ctrl_s),
+       .clk_gate_table_cnt =
+               sizeof(vpu_clk_gate_g12a) / sizeof(struct vpu_ctrl_s),
+       .mem_pd_table = vpu_mem_pd_tl1,
+       .clk_gate_table = vpu_clk_gate_g12a,
+
+       .module_init_table_cnt = 0,
+       .module_init_table = NULL,
+       .reset_table = vpu_reset_tl1,
 };
 
 static const struct of_device_id vpu_of_table[] = {
@@ -1421,6 +1499,10 @@ static const struct of_device_id vpu_of_table[] = {
                .compatible = "amlogic, vpu-g12b",
                .data = &vpu_data_g12b,
        },
+       {
+               .compatible = "amlogic, vpu-tl1",
+               .data = &vpu_data_tl1,
+       },
        {},
 };
 

diff --git a/drivers/amlogic/media/common/vpu/vpu.h b/drivers/amlogic/media/common/vpu/vpu.h
index 77e494e..997f96c 100644 (file)
--- a/drivers/amlogic/media/common/vpu/vpu.h
+++ b/drivers/amlogic/media/common/vpu/vpu.h
@@ -35,9 +35,13 @@ enum vpu_chip_e {
        VPU_CHIP_AXG,
        VPU_CHIP_G12A,
        VPU_CHIP_G12B,
+       VPU_CHIP_TL1,
        VPU_CHIP_MAX,
 };
 
+#define VPU_REG_END            0xffff
+#define VPU_RESET_CNT_MAX      10
+
 struct fclk_div_s {
        unsigned int fclk_id;
        unsigned int fclk_mux;
@@ -53,10 +57,16 @@ struct vpu_clk_s {
 struct vpu_ctrl_s {
        unsigned int vmod;
        unsigned int reg;
+       unsigned int val;
        unsigned int bit;
        unsigned int len;
 };
 
+struct vpu_reset_s {
+       unsigned int reg;
+       unsigned int mask;
+};
+
 struct vpu_data_s {
        enum vpu_chip_e chip_type;
        const char *chip_name;
@@ -67,14 +77,17 @@ struct vpu_data_s {
        unsigned char gp_pll_valid;
        unsigned char mem_pd_reg1_valid;
        unsigned char mem_pd_reg2_valid;
+       unsigned char mem_pd_reg3_valid;
+       unsigned char mem_pd_reg4_valid;
 
        unsigned int mem_pd_table_cnt;
        unsigned int clk_gate_table_cnt;
        struct vpu_ctrl_s *mem_pd_table;
        struct vpu_ctrl_s *clk_gate_table;
 
-       void (*power_on)(void);
-       void (*power_off)(void);
+       unsigned int module_init_table_cnt;
+       struct vpu_ctrl_s *module_init_table;
+       struct vpu_reset_s *reset_table;
 };
 
 struct vpu_conf_s {
@@ -102,11 +115,8 @@ extern int vpu_chip_valid_check(void);
 extern void vpu_ctrl_probe(void);
 
 extern void vpu_mem_pd_init_off(void);
-extern void vpu_clk_gate_init_off(void);
 extern void vpu_module_init_config(void);
-extern void vpu_power_on_gx(void);
-extern void vpu_power_off_gx(void);
-extern void vpu_power_on_txlx(void);
-extern void vpu_power_off_txlx(void);
+extern void vpu_power_on(void);
+extern void vpu_power_off(void);
 
 #endif

diff --git a/drivers/amlogic/media/common/vpu/vpu_ctrl.h b/drivers/amlogic/media/common/vpu/vpu_ctrl.h
index a38758d..ca0eb49 100644 (file)
--- a/drivers/amlogic/media/common/vpu/vpu_ctrl.h
+++ b/drivers/amlogic/media/common/vpu/vpu_ctrl.h
@@ -18,12 +18,11 @@
 #ifndef __VPU_CTRL_H__
 #define __VPU_CTRL_H__
 #include <linux/amlogic/media/vpu/vpu.h>
+#include "vpu_reg.h"
 #include "vpu.h"
 
 /* #define LIMIT_VPU_CLK_LOW */
 
-#define VPU_REG_END            0xffff
-
 /* ************************************************ */
 /* VPU frequency table, important. DO NOT modify!! */
 /* ************************************************ */
@@ -118,411 +117,526 @@ static struct vpu_clk_s vpu_clk_table[] = {
 /*              VPU memory power down table                */
 /* ******************************************************* */
 static struct vpu_ctrl_s vpu_mem_pd_gxb[] = {
-       /* vpu module,      reg,                  bit,  len */
-       {VPU_VIU_OSD1,      HHI_VPU_MEM_PD_REG0,   0,   2},
-       {VPU_VIU_OSD2,      HHI_VPU_MEM_PD_REG0,   2,   2},
-       {VPU_VIU_VD1,       HHI_VPU_MEM_PD_REG0,   4,   2},
-       {VPU_VIU_VD2,       HHI_VPU_MEM_PD_REG0,   6,   2},
-       {VPU_VIU_CHROMA,    HHI_VPU_MEM_PD_REG0,   8,   2},
-       {VPU_VIU_OFIFO,     HHI_VPU_MEM_PD_REG0,  10,   2},
-       {VPU_VIU_SCALE,     HHI_VPU_MEM_PD_REG0,  12,   2},
-       {VPU_VIU_OSD_SCALE, HHI_VPU_MEM_PD_REG0,  14,   2},
-       {VPU_VIU_VDIN0,     HHI_VPU_MEM_PD_REG0,  16,   2},
-       {VPU_VIU_VDIN1,     HHI_VPU_MEM_PD_REG0,  18,   2},
-       {VPU_VIU_SRSCL,     HHI_VPU_MEM_PD_REG0,  20,   2},
-       {VPU_VIU_OSDSR,     HHI_VPU_MEM_PD_REG0,  22,   2},
-       {VPU_DI_PRE,        HHI_VPU_MEM_PD_REG0,  26,   2},
-       {VPU_DI_POST,       HHI_VPU_MEM_PD_REG0,  28,   2},
-       {VPU_SHARP,         HHI_VPU_MEM_PD_REG0,  30,   2},
-       {VPU_VPU_ARB,       HHI_VPU_MEM_PD_REG1,  14,   2},
-       {VPU_AFBC_DEC,      HHI_VPU_MEM_PD_REG1,  16,   2},
-       {VPU_VENCP,         HHI_VPU_MEM_PD_REG1,  20,   2},
-       {VPU_VENCL,         HHI_VPU_MEM_PD_REG1,  22,   2},
-       {VPU_VENCI,         HHI_VPU_MEM_PD_REG1,  24,   2},
-       {VPU_MOD_MAX,       VPU_REG_END,           0,   0},
+       /* vpu module,      reg,                  val,  bit, len */
+       {VPU_VIU_OSD1,      HHI_VPU_MEM_PD_REG0,  0x3,  0,   2},
+       {VPU_VIU_OSD2,      HHI_VPU_MEM_PD_REG0,  0x3,  2,   2},
+       {VPU_VIU_VD1,       HHI_VPU_MEM_PD_REG0,  0x3,  4,   2},
+       {VPU_VIU_VD2,       HHI_VPU_MEM_PD_REG0,  0x3,  6,   2},
+       {VPU_VIU_CHROMA,    HHI_VPU_MEM_PD_REG0,  0x3,  8,   2},
+       {VPU_VIU_OFIFO,     HHI_VPU_MEM_PD_REG0,  0x3, 10,   2},
+       {VPU_VIU_SCALE,     HHI_VPU_MEM_PD_REG0,  0x3, 12,   2},
+       {VPU_VIU_OSD_SCALE, HHI_VPU_MEM_PD_REG0,  0x3, 14,   2},
+       {VPU_VIU_VDIN0,     HHI_VPU_MEM_PD_REG0,  0x3, 16,   2},
+       {VPU_VIU_VDIN1,     HHI_VPU_MEM_PD_REG0,  0x3, 18,   2},
+       {VPU_VIU_SRSCL,     HHI_VPU_MEM_PD_REG0,  0x3, 20,   2},
+       {VPU_VIU_OSDSR,     HHI_VPU_MEM_PD_REG0,  0x3, 22,   2},
+       {VPU_DI_PRE,        HHI_VPU_MEM_PD_REG0,  0x3, 26,   2},
+       {VPU_DI_POST,       HHI_VPU_MEM_PD_REG0,  0x3, 28,   2},
+       {VPU_SHARP,         HHI_VPU_MEM_PD_REG0,  0x3, 30,   2},
+       {VPU_VPU_ARB,       HHI_VPU_MEM_PD_REG1,  0x3, 14,   2},
+       {VPU_AFBC_DEC,      HHI_VPU_MEM_PD_REG1,  0x3, 16,   2},
+       {VPU_VENCP,         HHI_VPU_MEM_PD_REG1,  0x3, 20,   2},
+       {VPU_VENCL,         HHI_VPU_MEM_PD_REG1,  0x3, 22,   2},
+       {VPU_VENCI,         HHI_VPU_MEM_PD_REG1,  0x3, 24,   2},
+       {VPU_MOD_MAX,       VPU_REG_END,          0,    0,   0},
 };
 
 static struct vpu_ctrl_s vpu_mem_pd_gxtvbb[] = {
-       /* vpu module,      reg,                  bit,  len */
-       {VPU_VIU_OSD1,      HHI_VPU_MEM_PD_REG0,   0,   2},
-       {VPU_VIU_OSD2,      HHI_VPU_MEM_PD_REG0,   2,   2},
-       {VPU_VIU_VD1,       HHI_VPU_MEM_PD_REG0,   4,   2},
-       {VPU_VIU_VD2,       HHI_VPU_MEM_PD_REG0,   6,   2},
-       {VPU_VIU_CHROMA,    HHI_VPU_MEM_PD_REG0,   8,   2},
-       {VPU_VIU_OFIFO,     HHI_VPU_MEM_PD_REG0,  10,   2},
-       {VPU_VIU_SCALE,     HHI_VPU_MEM_PD_REG0,  12,   2},
-       {VPU_VIU_OSD_SCALE, HHI_VPU_MEM_PD_REG0,  14,   2},
-       {VPU_VIU_VDIN0,     HHI_VPU_MEM_PD_REG0,  16,   2},
-       {VPU_VIU_VDIN1,     HHI_VPU_MEM_PD_REG0,  18,   2},
-       {VPU_VIU_SRSCL,     HHI_VPU_MEM_PD_REG0,  20,   2},
-       {VPU_AFBC_DEC1,     HHI_VPU_MEM_PD_REG0,  22,   2},
-       {VPU_DI_PRE,        HHI_VPU_MEM_PD_REG0,  26,   2},
-       {VPU_DI_POST,       HHI_VPU_MEM_PD_REG0,  28,   2},
-       {VPU_SHARP,         HHI_VPU_MEM_PD_REG0,  30,   2},
-       {VPU_VPU_ARB,       HHI_VPU_MEM_PD_REG1,  14,   2},
-       {VPU_AFBC_DEC,      HHI_VPU_MEM_PD_REG1,  16,   2},
-       {VPU_VENCP,         HHI_VPU_MEM_PD_REG1,  20,   2},
-       {VPU_VENCL,         HHI_VPU_MEM_PD_REG1,  22,   2},
-       {VPU_VENCI,         HHI_VPU_MEM_PD_REG1,  24,   2},
-       {VPU_LDIM_STTS,     HHI_VPU_MEM_PD_REG1,  28,   2},
-       {VPU_XVYCC_LUT,     HHI_VPU_MEM_PD_REG1,  30,   2},
-       {VPU_MOD_MAX,       VPU_REG_END,           0,   0},
+       /* vpu module,      reg,                  val,  bit, len */
+       {VPU_VIU_OSD1,      HHI_VPU_MEM_PD_REG0,  0x3,  0,   2},
+       {VPU_VIU_OSD2,      HHI_VPU_MEM_PD_REG0,  0x3,  2,   2},
+       {VPU_VIU_VD1,       HHI_VPU_MEM_PD_REG0,  0x3,  4,   2},
+       {VPU_VIU_VD2,       HHI_VPU_MEM_PD_REG0,  0x3,  6,   2},
+       {VPU_VIU_CHROMA,    HHI_VPU_MEM_PD_REG0,  0x3,  8,   2},
+       {VPU_VIU_OFIFO,     HHI_VPU_MEM_PD_REG0,  0x3, 10,   2},
+       {VPU_VIU_SCALE,     HHI_VPU_MEM_PD_REG0,  0x3, 12,   2},
+       {VPU_VIU_OSD_SCALE, HHI_VPU_MEM_PD_REG0,  0x3, 14,   2},
+       {VPU_VIU_VDIN0,     HHI_VPU_MEM_PD_REG0,  0x3, 16,   2},
+       {VPU_VIU_VDIN1,     HHI_VPU_MEM_PD_REG0,  0x3, 18,   2},
+       {VPU_VIU_SRSCL,     HHI_VPU_MEM_PD_REG0,  0x3, 20,   2},
+       {VPU_AFBC_DEC1,     HHI_VPU_MEM_PD_REG0,  0x3, 22,   2},
+       {VPU_DI_PRE,        HHI_VPU_MEM_PD_REG0,  0x3, 26,   2},
+       {VPU_DI_POST,       HHI_VPU_MEM_PD_REG0,  0x3, 28,   2},
+       {VPU_SHARP,         HHI_VPU_MEM_PD_REG0,  0x3, 30,   2},
+       {VPU_VPU_ARB,       HHI_VPU_MEM_PD_REG1,  0x3, 14,   2},
+       {VPU_AFBC_DEC,      HHI_VPU_MEM_PD_REG1,  0x3, 16,   2},
+       {VPU_VENCP,         HHI_VPU_MEM_PD_REG1,  0x3, 20,   2},
+       {VPU_VENCL,         HHI_VPU_MEM_PD_REG1,  0x3, 22,   2},
+       {VPU_VENCI,         HHI_VPU_MEM_PD_REG1,  0x3, 24,   2},
+       {VPU_LDIM_STTS,     HHI_VPU_MEM_PD_REG1,  0x3, 28,   2},
+       {VPU_XVYCC_LUT,     HHI_VPU_MEM_PD_REG1,  0x3, 30,   2},
+       {VPU_MOD_MAX,       VPU_REG_END,          0,    0,   0},
 };
 
 static struct vpu_ctrl_s vpu_mem_pd_gxl[] = {
-       /* vpu module,      reg,                  bit,  len */
-       {VPU_VIU_OSD1,      HHI_VPU_MEM_PD_REG0,   0,   2},
-       {VPU_VIU_OSD2,      HHI_VPU_MEM_PD_REG0,   2,   2},
-       {VPU_VIU_VD1,       HHI_VPU_MEM_PD_REG0,   4,   2},
-       {VPU_VIU_VD2,       HHI_VPU_MEM_PD_REG0,   6,   2},
-       {VPU_VIU_CHROMA,    HHI_VPU_MEM_PD_REG0,   8,   2},
-       {VPU_VIU_OFIFO,     HHI_VPU_MEM_PD_REG0,  10,   2},
-       {VPU_VIU_SCALE,     HHI_VPU_MEM_PD_REG0,  12,   2},
-       {VPU_VIU_OSD_SCALE, HHI_VPU_MEM_PD_REG0,  14,   2},
-       {VPU_VIU_VDIN0,     HHI_VPU_MEM_PD_REG0,  16,   2},
-       {VPU_VIU_VDIN1,     HHI_VPU_MEM_PD_REG0,  18,   2},
-       {VPU_DI_PRE,        HHI_VPU_MEM_PD_REG0,  26,   2},
-       {VPU_DI_POST,       HHI_VPU_MEM_PD_REG0,  28,   2},
-       {VPU_SHARP,         HHI_VPU_MEM_PD_REG0,  30,   2},
-       {VPU_VPU_ARB,       HHI_VPU_MEM_PD_REG1,  14,   2},
-       {VPU_AFBC_DEC,      HHI_VPU_MEM_PD_REG1,  16,   2},
-       {VPU_VENCP,         HHI_VPU_MEM_PD_REG1,  20,   2},
-       {VPU_VENCL,         HHI_VPU_MEM_PD_REG1,  22,   2},
-       {VPU_VENCI,         HHI_VPU_MEM_PD_REG1,  24,   2},
-       {VPU_VIU_WM,        HHI_VPU_MEM_PD_REG2,   0,   2},
-       {VPU_MOD_MAX,       VPU_REG_END,           0,   0},
+       /* vpu module,      reg,                  val,  bit, len */
+       {VPU_VIU_OSD1,      HHI_VPU_MEM_PD_REG0,  0x3,  0,   2},
+       {VPU_VIU_OSD2,      HHI_VPU_MEM_PD_REG0,  0x3,  2,   2},
+       {VPU_VIU_VD1,       HHI_VPU_MEM_PD_REG0,  0x3,  4,   2},
+       {VPU_VIU_VD2,       HHI_VPU_MEM_PD_REG0,  0x3,  6,   2},
+       {VPU_VIU_CHROMA,    HHI_VPU_MEM_PD_REG0,  0x3,  8,   2},
+       {VPU_VIU_OFIFO,     HHI_VPU_MEM_PD_REG0,  0x3, 10,   2},
+       {VPU_VIU_SCALE,     HHI_VPU_MEM_PD_REG0,  0x3, 12,   2},
+       {VPU_VIU_OSD_SCALE, HHI_VPU_MEM_PD_REG0,  0x3, 14,   2},
+       {VPU_VIU_VDIN0,     HHI_VPU_MEM_PD_REG0,  0x3, 16,   2},
+       {VPU_VIU_VDIN1,     HHI_VPU_MEM_PD_REG0,  0x3, 18,   2},
+       {VPU_DI_PRE,        HHI_VPU_MEM_PD_REG0,  0x3, 26,   2},
+       {VPU_DI_POST,       HHI_VPU_MEM_PD_REG0,  0x3, 28,   2},
+       {VPU_SHARP,         HHI_VPU_MEM_PD_REG0,  0x3, 30,   2},
+       {VPU_VPU_ARB,       HHI_VPU_MEM_PD_REG1,  0x3, 14,   2},
+       {VPU_AFBC_DEC,      HHI_VPU_MEM_PD_REG1,  0x3, 16,   2},
+       {VPU_VENCP,         HHI_VPU_MEM_PD_REG1,  0x3, 20,   2},
+       {VPU_VENCL,         HHI_VPU_MEM_PD_REG1,  0x3, 22,   2},
+       {VPU_VENCI,         HHI_VPU_MEM_PD_REG1,  0x3, 24,   2},
+       {VPU_VIU_WM,        HHI_VPU_MEM_PD_REG2,  0x3,  0,   2},
+       {VPU_MOD_MAX,       VPU_REG_END,          0,    0,   0},
 };
 
 static struct vpu_ctrl_s vpu_mem_pd_txl[] = {
-       /* vpu module,      reg,                  bit,  len */
-       {VPU_VIU_OSD1,      HHI_VPU_MEM_PD_REG0,   0,   2},
-       {VPU_VIU_OSD2,      HHI_VPU_MEM_PD_REG0,   2,   2},
-       {VPU_VIU_VD1,       HHI_VPU_MEM_PD_REG0,   4,   2},
-       {VPU_VIU_VD2,       HHI_VPU_MEM_PD_REG0,   6,   2},
-       {VPU_VIU_CHROMA,    HHI_VPU_MEM_PD_REG0,   8,   2},
-       {VPU_VIU_OFIFO,     HHI_VPU_MEM_PD_REG0,  10,   2},
-       {VPU_VIU_SCALE,     HHI_VPU_MEM_PD_REG0,  12,   2},
-       {VPU_VIU_OSD_SCALE, HHI_VPU_MEM_PD_REG0,  14,   2},
-       {VPU_VIU_VDIN0,     HHI_VPU_MEM_PD_REG0,  16,   2},
-       {VPU_VIU_VDIN1,     HHI_VPU_MEM_PD_REG0,  18,   2},
-       {VPU_DI_PRE,        HHI_VPU_MEM_PD_REG0,  26,   2},
-       {VPU_DI_POST,       HHI_VPU_MEM_PD_REG0,  28,   2},
-       {VPU_SHARP,         HHI_VPU_MEM_PD_REG0,  30,   2},
-       {VPU_VPU_ARB,       HHI_VPU_MEM_PD_REG1,  14,   2},
-       {VPU_AFBC_DEC,      HHI_VPU_MEM_PD_REG1,  16,   2},
-       {VPU_VENCP,         HHI_VPU_MEM_PD_REG1,  20,   2},
-       {VPU_VENCL,         HHI_VPU_MEM_PD_REG1,  22,   2},
-       {VPU_VENCI,         HHI_VPU_MEM_PD_REG1,  24,   2},
-       {VPU_MOD_MAX,       VPU_REG_END,           0,   0},
+       /* vpu module,      reg,                  val,  bit, len */
+       {VPU_VIU_OSD1,      HHI_VPU_MEM_PD_REG0,  0x3,  0,   2},
+       {VPU_VIU_OSD2,      HHI_VPU_MEM_PD_REG0,  0x3,  2,   2},
+       {VPU_VIU_VD1,       HHI_VPU_MEM_PD_REG0,  0x3,  4,   2},
+       {VPU_VIU_VD2,       HHI_VPU_MEM_PD_REG0,  0x3,  6,   2},
+       {VPU_VIU_CHROMA,    HHI_VPU_MEM_PD_REG0,  0x3,  8,   2},
+       {VPU_VIU_OFIFO,     HHI_VPU_MEM_PD_REG0,  0x3, 10,   2},
+       {VPU_VIU_SCALE,     HHI_VPU_MEM_PD_REG0,  0x3, 12,   2},
+       {VPU_VIU_OSD_SCALE, HHI_VPU_MEM_PD_REG0,  0x3, 14,   2},
+       {VPU_VIU_VDIN0,     HHI_VPU_MEM_PD_REG0,  0x3, 16,   2},
+       {VPU_VIU_VDIN1,     HHI_VPU_MEM_PD_REG0,  0x3, 18,   2},
+       {VPU_DI_PRE,        HHI_VPU_MEM_PD_REG0,  0x3, 26,   2},
+       {VPU_DI_POST,       HHI_VPU_MEM_PD_REG0,  0x3, 28,   2},
+       {VPU_SHARP,         HHI_VPU_MEM_PD_REG0,  0x3, 30,   2},
+       {VPU_VPU_ARB,       HHI_VPU_MEM_PD_REG1,  0x3, 14,   2},
+       {VPU_AFBC_DEC,      HHI_VPU_MEM_PD_REG1,  0x3, 16,   2},
+       {VPU_VENCP,         HHI_VPU_MEM_PD_REG1,  0x3, 20,   2},
+       {VPU_VENCL,         HHI_VPU_MEM_PD_REG1,  0x3, 22,   2},
+       {VPU_VENCI,         HHI_VPU_MEM_PD_REG1,  0x3, 24,   2},
+       {VPU_MOD_MAX,       VPU_REG_END,          0,    0,   0},
 };
 
 static struct vpu_ctrl_s vpu_mem_pd_txlx[] = {
-       /* vpu module,      reg,                  bit,  len */
-       {VPU_VIU_OSD1,      HHI_VPU_MEM_PD_REG0,   0,   2},
-       {VPU_VIU_OSD2,      HHI_VPU_MEM_PD_REG0,   2,   2},
-       {VPU_VIU_VD1,       HHI_VPU_MEM_PD_REG0,   4,   2},
-       {VPU_VIU_VD2,       HHI_VPU_MEM_PD_REG0,   6,   2},
-       {VPU_VIU_CHROMA,    HHI_VPU_MEM_PD_REG0,   8,   2},
-       {VPU_VIU_OFIFO,     HHI_VPU_MEM_PD_REG0,  10,   2},
-       {VPU_VIU_SCALE,     HHI_VPU_MEM_PD_REG0,  12,   2},
-       {VPU_VIU_OSD_SCALE, HHI_VPU_MEM_PD_REG0,  14,   2},
-       {VPU_VIU_VDIN0,     HHI_VPU_MEM_PD_REG0,  16,   2},
-       {VPU_VIU_VDIN1,     HHI_VPU_MEM_PD_REG0,  18,   2},
-       {VPU_VIU_SRSCL,     HHI_VPU_MEM_PD_REG0,  20,   2},
-       {VPU_AFBC_DEC1,     HHI_VPU_MEM_PD_REG0,  22,   2},
-       {VPU_DI_PRE,        HHI_VPU_MEM_PD_REG0,  26,   2},
-       {VPU_DI_POST,       HHI_VPU_MEM_PD_REG0,  28,   2},
-       {VPU_SHARP,         HHI_VPU_MEM_PD_REG0,  30,   2},
-       {VPU_VKSTONE,       HHI_VPU_MEM_PD_REG1,   4,   2},
-       {VPU_DOLBY_CORE3,   HHI_VPU_MEM_PD_REG1,   6,   2},
-       {VPU_DOLBY0,        HHI_VPU_MEM_PD_REG1,   8,   2},
-       {VPU_DOLBY1A,       HHI_VPU_MEM_PD_REG1,  10,   2},
-       {VPU_DOLBY1B,       HHI_VPU_MEM_PD_REG1,  12,   2},
-       {VPU_VPU_ARB,       HHI_VPU_MEM_PD_REG1,  14,   2},
-       {VPU_AFBC_DEC,      HHI_VPU_MEM_PD_REG1,  16,   2},
-       {VPU_OSD_AFBCD,     HHI_VPU_MEM_PD_REG1,  18,   2},
-       {VPU_VENCP,         HHI_VPU_MEM_PD_REG1,  20,   2},
-       {VPU_VENCL,         HHI_VPU_MEM_PD_REG1,  22,   2},
-       {VPU_VENCI,         HHI_VPU_MEM_PD_REG1,  24,   2},
-       {VPU_LDIM_STTS,     HHI_VPU_MEM_PD_REG1,  28,   2},
-       {VPU_XVYCC_LUT,     HHI_VPU_MEM_PD_REG1,  30,   2},
-       {VPU_VIU_WM,        HHI_VPU_MEM_PD_REG2,   0,   2},
-       {VPU_MOD_MAX,       VPU_REG_END,           0,   0},
+       /* vpu module,      reg,                  val,  bit, len */
+       {VPU_VIU_OSD1,      HHI_VPU_MEM_PD_REG0,  0x3,  0,   2},
+       {VPU_VIU_OSD2,      HHI_VPU_MEM_PD_REG0,  0x3,  2,   2},
+       {VPU_VIU_VD1,       HHI_VPU_MEM_PD_REG0,  0x3,  4,   2},
+       {VPU_VIU_VD2,       HHI_VPU_MEM_PD_REG0,  0x3,  6,   2},
+       {VPU_VIU_CHROMA,    HHI_VPU_MEM_PD_REG0,  0x3,  8,   2},
+       {VPU_VIU_OFIFO,     HHI_VPU_MEM_PD_REG0,  0x3, 10,   2},
+       {VPU_VIU_SCALE,     HHI_VPU_MEM_PD_REG0,  0x3, 12,   2},
+       {VPU_VIU_OSD_SCALE, HHI_VPU_MEM_PD_REG0,  0x3, 14,   2},
+       {VPU_VIU_VDIN0,     HHI_VPU_MEM_PD_REG0,  0x3, 16,   2},
+       {VPU_VIU_VDIN1,     HHI_VPU_MEM_PD_REG0,  0x3, 18,   2},
+       {VPU_VIU_SRSCL,     HHI_VPU_MEM_PD_REG0,  0x3, 20,   2},
+       {VPU_AFBC_DEC1,     HHI_VPU_MEM_PD_REG0,  0x3, 22,   2},
+       {VPU_DI_PRE,        HHI_VPU_MEM_PD_REG0,  0x3, 26,   2},
+       {VPU_DI_POST,       HHI_VPU_MEM_PD_REG0,  0x3, 28,   2},
+       {VPU_SHARP,         HHI_VPU_MEM_PD_REG0,  0x3, 30,   2},
+       {VPU_VKSTONE,       HHI_VPU_MEM_PD_REG1,  0x3,  4,   2},
+       {VPU_DOLBY_CORE3,   HHI_VPU_MEM_PD_REG1,  0x3,  6,   2},
+       {VPU_DOLBY0,        HHI_VPU_MEM_PD_REG1,  0x3,  8,   2},
+       {VPU_DOLBY1A,       HHI_VPU_MEM_PD_REG1,  0x3, 10,   2},
+       {VPU_DOLBY1B,       HHI_VPU_MEM_PD_REG1,  0x3, 12,   2},
+       {VPU_VPU_ARB,       HHI_VPU_MEM_PD_REG1,  0x3, 14,   2},
+       {VPU_AFBC_DEC,      HHI_VPU_MEM_PD_REG1,  0x3, 16,   2},
+       {VPU_OSD_AFBCD,     HHI_VPU_MEM_PD_REG1,  0x3, 18,   2},
+       {VPU_VENCP,         HHI_VPU_MEM_PD_REG1,  0x3, 20,   2},
+       {VPU_VENCL,         HHI_VPU_MEM_PD_REG1,  0x3, 22,   2},
+       {VPU_VENCI,         HHI_VPU_MEM_PD_REG1,  0x3, 24,   2},
+       {VPU_LDIM_STTS,     HHI_VPU_MEM_PD_REG1,  0x3, 28,   2},
+       {VPU_XVYCC_LUT,     HHI_VPU_MEM_PD_REG1,  0x3, 30,   2},
+       {VPU_VIU_WM,        HHI_VPU_MEM_PD_REG2,  0x3,  0,   2},
+       {VPU_MOD_MAX,       VPU_REG_END,          0,    0,   0},
 };
 
 static struct vpu_ctrl_s vpu_mem_pd_axg[] = {
-       /* vpu module,      reg,                  bit,  len */
-       {VPU_VIU_OSD1,      HHI_VPU_MEM_PD_REG0,   0,   2},
-       {VPU_VIU_OFIFO,     HHI_VPU_MEM_PD_REG0,   2,   2},
-       {VPU_VPU_ARB,       HHI_VPU_MEM_PD_REG0,   4,   2},
-       {VPU_VENCL,         HHI_VPU_MEM_PD_REG0,   6,   2},
-       {VPU_MOD_MAX,       VPU_REG_END,           0,   0},
+       /* vpu module,      reg,                  val, bit, len */
+       {VPU_VIU_OSD1,      HHI_VPU_MEM_PD_REG0,  0x3, 0,   2},
+       {VPU_VIU_OFIFO,     HHI_VPU_MEM_PD_REG0,  0x3, 2,   2},
+       {VPU_VPU_ARB,       HHI_VPU_MEM_PD_REG0,  0x3, 4,   2},
+       {VPU_VENCL,         HHI_VPU_MEM_PD_REG0,  0x3, 6,   2},
+       {VPU_MOD_MAX,       VPU_REG_END,          0,   0,   0},
 };
 
 static struct vpu_ctrl_s vpu_mem_pd_g12a[] = {
-       /* vpu module,      reg,                  bit,  len */
-       {VPU_VIU_OSD1,        HHI_VPU_MEM_PD_REG0,   0,   2},
-       {VPU_VIU_OSD2,        HHI_VPU_MEM_PD_REG0,   2,   2},
-       {VPU_VIU_VD1,         HHI_VPU_MEM_PD_REG0,   4,   2},
-       {VPU_VIU_VD2,         HHI_VPU_MEM_PD_REG0,   6,   2},
-       {VPU_VIU_CHROMA,      HHI_VPU_MEM_PD_REG0,   8,   2},
-       {VPU_VIU_OFIFO,       HHI_VPU_MEM_PD_REG0,  10,   2},
-       {VPU_VIU_SCALE,       HHI_VPU_MEM_PD_REG0,  12,   2},
-       {VPU_VIU_OSD_SCALE,   HHI_VPU_MEM_PD_REG0,  14,   2},
-       {VPU_VIU_VDIN0,       HHI_VPU_MEM_PD_REG0,  16,   2},
-       {VPU_VIU_VDIN1,       HHI_VPU_MEM_PD_REG0,  18,   2},
-       {VPU_VIU_SRSCL,       HHI_VPU_MEM_PD_REG0,  20,   2},
-       {VPU_AFBC_DEC1,       HHI_VPU_MEM_PD_REG0,  22,   2},
-       {VPU_VIU_DI_SCALE,    HHI_VPU_MEM_PD_REG0,  24,   2},
-       {VPU_DI_PRE,          HHI_VPU_MEM_PD_REG0,  26,   2},
-       {VPU_DI_POST,         HHI_VPU_MEM_PD_REG0,  28,   2},
-       {VPU_SHARP,           HHI_VPU_MEM_PD_REG0,  30,   2},
-       {VPU_VIU2_OSD1,       HHI_VPU_MEM_PD_REG1,   0,   2},
-       {VPU_VIU2_OFIFO,      HHI_VPU_MEM_PD_REG1,   2,   2},
-       {VPU_VKSTONE,         HHI_VPU_MEM_PD_REG1,   4,   2},
-       {VPU_DOLBY_CORE3,     HHI_VPU_MEM_PD_REG1,   6,   2},
-       {VPU_DOLBY0,          HHI_VPU_MEM_PD_REG1,   8,   2},
-       {VPU_DOLBY1A,         HHI_VPU_MEM_PD_REG1,  10,   2},
-       {VPU_DOLBY1B,         HHI_VPU_MEM_PD_REG1,  12,   2},
-       {VPU_VPU_ARB,         HHI_VPU_MEM_PD_REG1,  14,   2},
-       {VPU_AFBC_DEC,        HHI_VPU_MEM_PD_REG1,  16,   2},
-       {VPU_VD2_SCALE,       HHI_VPU_MEM_PD_REG1,  18,   2},
-       {VPU_VENCP,           HHI_VPU_MEM_PD_REG1,  20,   2},
-       {VPU_VENCL,           HHI_VPU_MEM_PD_REG1,  22,   2},
-       {VPU_VENCI,           HHI_VPU_MEM_PD_REG1,  24,   2},
-       {VPU_VD2_OSD2_SCALE,  HHI_VPU_MEM_PD_REG1,  30,   2},
-       {VPU_VIU_WM,          HHI_VPU_MEM_PD_REG2,   0,   2},
-       {VPU_VIU_OSD3,        HHI_VPU_MEM_PD_REG2,   4,   2},
-       {VPU_VIU_OSD4,        HHI_VPU_MEM_PD_REG2,   6,   2},
-       {VPU_MAIL_AFBCD,      HHI_VPU_MEM_PD_REG2,   8,   2},
-       {VPU_VD1_SCALE,       HHI_VPU_MEM_PD_REG2,  10,   2},
-       {VPU_OSD_BLD34,       HHI_VPU_MEM_PD_REG2,  12,   2},
-       {VPU_PRIME_DOLBY_RAM, HHI_VPU_MEM_PD_REG2,  14,   2},
-       {VPU_VD2_OFIFO,       HHI_VPU_MEM_PD_REG2,  16,   2},
-       {VPU_RDMA,            HHI_VPU_MEM_PD_REG2,  30,   2},
-       {VPU_MOD_MAX,         VPU_REG_END,           0,   0},
+       /* vpu module,      reg,                   val,  bit, len */
+       {VPU_VIU_OSD1,        HHI_VPU_MEM_PD_REG0, 0x3,  0,   2},
+       {VPU_VIU_OSD2,        HHI_VPU_MEM_PD_REG0, 0x3,  2,   2},
+       {VPU_VIU_VD1,         HHI_VPU_MEM_PD_REG0, 0x3,  4,   2},
+       {VPU_VIU_VD2,         HHI_VPU_MEM_PD_REG0, 0x3,  6,   2},
+       {VPU_VIU_CHROMA,      HHI_VPU_MEM_PD_REG0, 0x3,  8,   2},
+       {VPU_VIU_OFIFO,       HHI_VPU_MEM_PD_REG0, 0x3, 10,   2},
+       {VPU_VIU_SCALE,       HHI_VPU_MEM_PD_REG0, 0x3, 12,   2},
+       {VPU_VIU_OSD_SCALE,   HHI_VPU_MEM_PD_REG0, 0x3, 14,   2},
+       {VPU_VIU_VDIN0,       HHI_VPU_MEM_PD_REG0, 0x3, 16,   2},
+       {VPU_VIU_VDIN1,       HHI_VPU_MEM_PD_REG0, 0x3, 18,   2},
+       {VPU_VIU_SRSCL,       HHI_VPU_MEM_PD_REG0, 0x3, 20,   2},
+       {VPU_AFBC_DEC1,       HHI_VPU_MEM_PD_REG0, 0x3, 22,   2},
+       {VPU_VIU_DI_SCALE,    HHI_VPU_MEM_PD_REG0, 0x3, 24,   2},
+       {VPU_DI_PRE,          HHI_VPU_MEM_PD_REG0, 0x3, 26,   2},
+       {VPU_DI_POST,         HHI_VPU_MEM_PD_REG0, 0x3, 28,   2},
+       {VPU_SHARP,           HHI_VPU_MEM_PD_REG0, 0x3, 30,   2},
+       {VPU_VIU2_OSD1,       HHI_VPU_MEM_PD_REG1, 0x3,  0,   2},
+       {VPU_VIU2_OFIFO,      HHI_VPU_MEM_PD_REG1, 0x3,  2,   2},
+       {VPU_VKSTONE,         HHI_VPU_MEM_PD_REG1, 0x3,  4,   2},
+       {VPU_DOLBY_CORE3,     HHI_VPU_MEM_PD_REG1, 0x3,  6,   2},
+       {VPU_DOLBY0,          HHI_VPU_MEM_PD_REG1, 0x3,  8,   2},
+       {VPU_DOLBY1A,         HHI_VPU_MEM_PD_REG1, 0x3, 10,   2},
+       {VPU_DOLBY1B,         HHI_VPU_MEM_PD_REG1, 0x3, 12,   2},
+       {VPU_VPU_ARB,         HHI_VPU_MEM_PD_REG1, 0x3, 14,   2},
+       {VPU_AFBC_DEC,        HHI_VPU_MEM_PD_REG1, 0x3, 16,   2},
+       {VPU_VD2_SCALE,       HHI_VPU_MEM_PD_REG1, 0x3, 18,   2},
+       {VPU_VENCP,           HHI_VPU_MEM_PD_REG1, 0x3, 20,   2},
+       {VPU_VENCL,           HHI_VPU_MEM_PD_REG1, 0x3, 22,   2},
+       {VPU_VENCI,           HHI_VPU_MEM_PD_REG1, 0x3, 24,   2},
+       {VPU_VD2_OSD2_SCALE,  HHI_VPU_MEM_PD_REG1, 0x3, 30,   2},
+       {VPU_VIU_WM,          HHI_VPU_MEM_PD_REG2, 0x3,  0,   2},
+       {VPU_VIU_OSD3,        HHI_VPU_MEM_PD_REG2, 0x3,  4,   2},
+       {VPU_VIU_OSD4,        HHI_VPU_MEM_PD_REG2, 0x3,  6,   2},
+       {VPU_MAIL_AFBCD,      HHI_VPU_MEM_PD_REG2, 0x3,  8,   2},
+       {VPU_VD1_SCALE,       HHI_VPU_MEM_PD_REG2, 0x3, 10,   2},
+       {VPU_OSD_BLD34,       HHI_VPU_MEM_PD_REG2, 0x3, 12,   2},
+       {VPU_PRIME_DOLBY_RAM, HHI_VPU_MEM_PD_REG2, 0x3, 14,   2},
+       {VPU_VD2_OFIFO,       HHI_VPU_MEM_PD_REG2, 0x3, 16,   2},
+       {VPU_RDMA,            HHI_VPU_MEM_PD_REG2, 0x3, 30,   2},
+       {VPU_MOD_MAX,         VPU_REG_END,         0,    0,   0},
 };
 
 static struct vpu_ctrl_s vpu_mem_pd_g12b[] = {
-       /* vpu module,      reg,                  bit,  len */
-       {VPU_VIU_OSD1,        HHI_VPU_MEM_PD_REG0,   0,   2},
-       {VPU_VIU_OSD2,        HHI_VPU_MEM_PD_REG0,   2,   2},
-       {VPU_VIU_VD1,         HHI_VPU_MEM_PD_REG0,   4,   2},
-       {VPU_VIU_VD2,         HHI_VPU_MEM_PD_REG0,   6,   2},
-       {VPU_VIU_CHROMA,      HHI_VPU_MEM_PD_REG0,   8,   2},
-       {VPU_VIU_OFIFO,       HHI_VPU_MEM_PD_REG0,  10,   2},
-       {VPU_VIU_SCALE,       HHI_VPU_MEM_PD_REG0,  12,   2},
-       {VPU_VIU_OSD_SCALE,   HHI_VPU_MEM_PD_REG0,  14,   2},
-       {VPU_VIU_VDIN0,       HHI_VPU_MEM_PD_REG0,  16,   2},
-       {VPU_VIU_VDIN1,       HHI_VPU_MEM_PD_REG0,  18,   2},
-       {VPU_VIU_SRSCL,       HHI_VPU_MEM_PD_REG0,  20,   2},
-       {VPU_AFBC_DEC1,       HHI_VPU_MEM_PD_REG0,  22,   2},
-       {VPU_VIU_DI_SCALE,    HHI_VPU_MEM_PD_REG0,  24,   2},
-       {VPU_DI_PRE,          HHI_VPU_MEM_PD_REG0,  26,   2},
-       {VPU_DI_POST,         HHI_VPU_MEM_PD_REG0,  28,   2},
-       {VPU_SHARP,           HHI_VPU_MEM_PD_REG0,  30,   2},
-       {VPU_VIU2_OSD1,       HHI_VPU_MEM_PD_REG1,   0,   2},
-       {VPU_VIU2_OFIFO,      HHI_VPU_MEM_PD_REG1,   2,   2},
-       {VPU_VKSTONE,         HHI_VPU_MEM_PD_REG1,   4,   2},
-       {VPU_DOLBY_CORE3,     HHI_VPU_MEM_PD_REG1,   6,   2},
-       {VPU_DOLBY0,          HHI_VPU_MEM_PD_REG1,   8,   2},
-       {VPU_DOLBY1A,         HHI_VPU_MEM_PD_REG1,  10,   2},
-       {VPU_DOLBY1B,         HHI_VPU_MEM_PD_REG1,  12,   2},
-       {VPU_VPU_ARB,         HHI_VPU_MEM_PD_REG1,  14,   2},
-       {VPU_AFBC_DEC,        HHI_VPU_MEM_PD_REG1,  16,   2},
-       {VPU_VD2_SCALE,       HHI_VPU_MEM_PD_REG1,  18,   2},
-       {VPU_VENCP,           HHI_VPU_MEM_PD_REG1,  20,   2},
-       {VPU_VENCL,           HHI_VPU_MEM_PD_REG1,  22,   2},
-       {VPU_VENCI,           HHI_VPU_MEM_PD_REG1,  24,   2},
-       {VPU_VD2_OSD2_SCALE,  HHI_VPU_MEM_PD_REG1,  30,   2},
-       {VPU_VIU_WM,          HHI_VPU_MEM_PD_REG2,   0,   2},
-       {VPU_VIU_OSD3,        HHI_VPU_MEM_PD_REG2,   4,   2},
-       {VPU_VIU_OSD4,        HHI_VPU_MEM_PD_REG2,   6,   2},
-       {VPU_MAIL_AFBCD,      HHI_VPU_MEM_PD_REG2,   8,   2},
-       {VPU_VD1_SCALE,       HHI_VPU_MEM_PD_REG2,  10,   2},
-       {VPU_OSD_BLD34,       HHI_VPU_MEM_PD_REG2,  12,   2},
-       {VPU_PRIME_DOLBY_RAM, HHI_VPU_MEM_PD_REG2,  14,   2},
-       {VPU_VD2_OFIFO,       HHI_VPU_MEM_PD_REG2,  16,   2},
-       {VPU_LUT3D,           HHI_VPU_MEM_PD_REG2,  20,   2},
-       {VPU_VIU2_OSD_ROT,    HHI_VPU_MEM_PD_REG2,  22,   2},
-       {VPU_RDMA,            HHI_VPU_MEM_PD_REG2,  30,   2},
-       {VPU_MOD_MAX,         VPU_REG_END,           0,   0},
+       /* vpu module,      reg,                   val,  bit, len */
+       {VPU_VIU_OSD1,        HHI_VPU_MEM_PD_REG0, 0x3,  0,   2},
+       {VPU_VIU_OSD2,        HHI_VPU_MEM_PD_REG0, 0x3,  2,   2},
+       {VPU_VIU_VD1,         HHI_VPU_MEM_PD_REG0, 0x3,  4,   2},
+       {VPU_VIU_VD2,         HHI_VPU_MEM_PD_REG0, 0x3,  6,   2},
+       {VPU_VIU_CHROMA,      HHI_VPU_MEM_PD_REG0, 0x3,  8,   2},
+       {VPU_VIU_OFIFO,       HHI_VPU_MEM_PD_REG0, 0x3, 10,   2},
+       {VPU_VIU_SCALE,       HHI_VPU_MEM_PD_REG0, 0x3, 12,   2},
+       {VPU_VIU_OSD_SCALE,   HHI_VPU_MEM_PD_REG0, 0x3, 14,   2},
+       {VPU_VIU_VDIN0,       HHI_VPU_MEM_PD_REG0, 0x3, 16,   2},
+       {VPU_VIU_VDIN1,       HHI_VPU_MEM_PD_REG0, 0x3, 18,   2},
+       {VPU_VIU_SRSCL,       HHI_VPU_MEM_PD_REG0, 0x3, 20,   2},
+       {VPU_AFBC_DEC1,       HHI_VPU_MEM_PD_REG0, 0x3, 22,   2},
+       {VPU_VIU_DI_SCALE,    HHI_VPU_MEM_PD_REG0, 0x3, 24,   2},
+       {VPU_DI_PRE,          HHI_VPU_MEM_PD_REG0, 0x3, 26,   2},
+       {VPU_DI_POST,         HHI_VPU_MEM_PD_REG0, 0x3, 28,   2},
+       {VPU_SHARP,           HHI_VPU_MEM_PD_REG0, 0x3, 30,   2},
+       {VPU_VIU2_OSD1,       HHI_VPU_MEM_PD_REG1, 0x3,  0,   2},
+       {VPU_VIU2_OFIFO,      HHI_VPU_MEM_PD_REG1, 0x3,  2,   2},
+       {VPU_VKSTONE,         HHI_VPU_MEM_PD_REG1, 0x3,  4,   2},
+       {VPU_DOLBY_CORE3,     HHI_VPU_MEM_PD_REG1, 0x3,  6,   2},
+       {VPU_DOLBY0,          HHI_VPU_MEM_PD_REG1, 0x3,  8,   2},
+       {VPU_DOLBY1A,         HHI_VPU_MEM_PD_REG1, 0x3, 10,   2},
+       {VPU_DOLBY1B,         HHI_VPU_MEM_PD_REG1, 0x3, 12,   2},
+       {VPU_VPU_ARB,         HHI_VPU_MEM_PD_REG1, 0x3, 14,   2},
+       {VPU_AFBC_DEC,        HHI_VPU_MEM_PD_REG1, 0x3, 16,   2},
+       {VPU_VD2_SCALE,       HHI_VPU_MEM_PD_REG1, 0x3, 18,   2},
+       {VPU_VENCP,           HHI_VPU_MEM_PD_REG1, 0x3, 20,   2},
+       {VPU_VENCL,           HHI_VPU_MEM_PD_REG1, 0x3, 22,   2},
+       {VPU_VENCI,           HHI_VPU_MEM_PD_REG1, 0x3, 24,   2},
+       {VPU_VD2_OSD2_SCALE,  HHI_VPU_MEM_PD_REG1, 0x3, 30,   2},
+       {VPU_VIU_WM,          HHI_VPU_MEM_PD_REG2, 0x3,  0,   2},
+       {VPU_VIU_OSD3,        HHI_VPU_MEM_PD_REG2, 0x3,  4,   2},
+       {VPU_VIU_OSD4,        HHI_VPU_MEM_PD_REG2, 0x3,  6,   2},
+       {VPU_MAIL_AFBCD,      HHI_VPU_MEM_PD_REG2, 0x3,  8,   2},
+       {VPU_VD1_SCALE,       HHI_VPU_MEM_PD_REG2, 0x3, 10,   2},
+       {VPU_OSD_BLD34,       HHI_VPU_MEM_PD_REG2, 0x3, 12,   2},
+       {VPU_PRIME_DOLBY_RAM, HHI_VPU_MEM_PD_REG2, 0x3, 14,   2},
+       {VPU_VD2_OFIFO,       HHI_VPU_MEM_PD_REG2, 0x3, 16,   2},
+       {VPU_LUT3D,           HHI_VPU_MEM_PD_REG2, 0x3, 20,   2},
+       {VPU_VIU2_OSD_ROT,    HHI_VPU_MEM_PD_REG2, 0x3, 22,   2},
+       {VPU_RDMA,            HHI_VPU_MEM_PD_REG2, 0x3, 30,   2},
+       {VPU_MOD_MAX,         VPU_REG_END,         0,    0,   0},
+};
+
+static struct vpu_ctrl_s vpu_mem_pd_tl1[] = {
+       /* vpu module,        reg,                 val,  bit, len */
+       {VPU_VIU_OSD1,        HHI_VPU_MEM_PD_REG0, 0x3,  0,   2},
+       {VPU_VIU_OSD2,        HHI_VPU_MEM_PD_REG0, 0x3,  2,   2},
+       {VPU_VIU_VD1,         HHI_VPU_MEM_PD_REG0, 0x3,  4,   2},
+       {VPU_VIU_VD2,         HHI_VPU_MEM_PD_REG0, 0x3,  6,   2},
+       {VPU_VIU_CHROMA,      HHI_VPU_MEM_PD_REG0, 0x3,  8,   2},
+       {VPU_VIU_OFIFO,       HHI_VPU_MEM_PD_REG0, 0x3, 10,   2},
+       {VPU_VIU_SCALE,       HHI_VPU_MEM_PD_REG0, 0x3, 12,   2},
+       {VPU_VIU_OSD_SCALE,   HHI_VPU_MEM_PD_REG0, 0x3, 14,   2},
+       {VPU_VIU_VDIN0,       HHI_VPU_MEM_PD_REG0, 0x3, 16,   2},
+       {VPU_VIU_VDIN1,       HHI_VPU_MEM_PD_REG0, 0x3, 18,   2},
+       {VPU_VIU_SRSCL,       HHI_VPU_MEM_PD_REG0, 0x3, 20,   2},
+       {VPU_AFBC_DEC1,       HHI_VPU_MEM_PD_REG0, 0x3, 22,   2},
+       {VPU_VIU_DI_SCALE,    HHI_VPU_MEM_PD_REG0, 0x3, 24,   2},
+       {VPU_DI_PRE,          HHI_VPU_MEM_PD_REG0, 0x3, 26,   2},
+       {VPU_DI_POST,         HHI_VPU_MEM_PD_REG0, 0x3, 28,   2},
+       {VPU_SHARP,           HHI_VPU_MEM_PD_REG0, 0x3, 30,   2},
+       {VPU_VIU2_OSD1,       HHI_VPU_MEM_PD_REG1, 0x3,  0,   2},
+       {VPU_VIU2_OFIFO,      HHI_VPU_MEM_PD_REG1, 0x3,  2,   2},
+       {VPU_VKSTONE,         HHI_VPU_MEM_PD_REG1, 0x3,  4,   2},
+       {VPU_DOLBY_CORE3,     HHI_VPU_MEM_PD_REG1, 0x3,  6,   2},
+       {VPU_DOLBY0,          HHI_VPU_MEM_PD_REG1, 0x3,  8,   2},
+       {VPU_DOLBY1A,         HHI_VPU_MEM_PD_REG1, 0x3, 10,   2},
+       {VPU_DOLBY1B,         HHI_VPU_MEM_PD_REG1, 0x3, 12,   2},
+       {VPU_VPU_ARB,         HHI_VPU_MEM_PD_REG1, 0x3, 14,   2},
+       {VPU_AFBC_DEC,        HHI_VPU_MEM_PD_REG1, 0x3, 16,   2},
+       {VPU_VD2_SCALE,       HHI_VPU_MEM_PD_REG1, 0x3, 18,   2},
+       {VPU_VENCP,           HHI_VPU_MEM_PD_REG1, 0x3, 20,   2},
+       {VPU_VENCL,           HHI_VPU_MEM_PD_REG1, 0x3, 22,   2},
+       {VPU_VENCI,           HHI_VPU_MEM_PD_REG1, 0x3, 24,   2},
+       {VPU_LS_STTS,         HHI_VPU_MEM_PD_REG1, 0x3, 26,   2},
+       {VPU_LDIM_STTS,       HHI_VPU_MEM_PD_REG1, 0x3, 28,   2},
+       {VPU_VD2_OSD2_SCALE,  HHI_VPU_MEM_PD_REG1, 0x3, 30,   2},
+       {VPU_VIU_WM,          HHI_VPU_MEM_PD_REG2, 0x3,  0,   2},
+       {VPU_TCON,            HHI_VPU_MEM_PD_REG2, 0x3,  2,   2},
+       {VPU_VIU_OSD3,        HHI_VPU_MEM_PD_REG2, 0x3,  4,   2},
+       {VPU_VIU_OSD4,        HHI_VPU_MEM_PD_REG2, 0x3,  6,   2},
+       {VPU_MAIL_AFBCD,      HHI_VPU_MEM_PD_REG2, 0x3,  8,   2},
+       {VPU_VD1_SCALE,       HHI_VPU_MEM_PD_REG2, 0x3, 10,   2},
+       {VPU_OSD_BLD34,       HHI_VPU_MEM_PD_REG2, 0x3, 12,   2},
+       {VPU_PRIME_DOLBY_RAM, HHI_VPU_MEM_PD_REG2, 0x3, 14,   2},
+       {VPU_VD2_OFIFO,       HHI_VPU_MEM_PD_REG2, 0x3, 16,   2},
+       {VPU_DS,              HHI_VPU_MEM_PD_REG2, 0x3, 18,   2},
+       {VPU_LUT3D,           HHI_VPU_MEM_PD_REG2, 0x3, 20,   2},
+       {VPU_VIU2_OSD_ROT,    HHI_VPU_MEM_PD_REG2, 0x3, 22,   2},
+       {VPU_VI_DIPRE,        HHI_VPU_MEM_PD_REG2, 0xf, 24,   4},
+       {VPU_RDMA,            HHI_VPU_MEM_PD_REG2, 0x3, 30,   2},
+       {VPU_TCON,            HHI_VPU_MEM_PD_REG3, 0x3,  0,  16},
+       {VPU_TCON,            HHI_VPU_MEM_PD_REG3, 0x3, 16,  16},
+       {VPU_AXI_WR1,         HHI_VPU_MEM_PD_REG4, 0x3,  0,   2},
+       {VPU_AXI_WR0,         HHI_VPU_MEM_PD_REG4, 0x3,  2,   2},
+       {VPU_AFBCE,           HHI_VPU_MEM_PD_REG4, 0x3,  4,   2},
+       {VPU_MOD_MAX,         VPU_REG_END,         0,    0,   0},
 };
 
 /* ******************************************************* */
 /*                 VPU clock gate table                    */
 /* ******************************************************* */
 static struct vpu_ctrl_s vpu_clk_gate_gxb[] = {
-       /* vpu module,      reg,                  bit,  len */
-       {VPU_VPU_TOP,       VPU_CLK_GATE,          1,   1}, /* vpu_system_clk */
-       {VPU_VPU_CLKB,      VPU_CLK_GATE,         16,   1},
-       {VPU_RDMA,          VPU_CLK_GATE,         15,   1}, /* rdma_clk */
-       {VPU_VLOCK,         VPU_CLK_GATE,         14,   1},
-       {VPU_MISC,          VPU_CLK_GATE,          6,   1}, /* hs,vs interrupt*/
-       {VPU_VENCP,         VPU_CLK_GATE,          3,   1},
-       {VPU_VENCP,         VPU_CLK_GATE,          0,   1},
-       {VPU_VENCL,         VPU_CLK_GATE,          4,   2},
-       {VPU_VENCI,         VPU_CLK_GATE,         10,   2},
-       {VPU_VIU_VDIN0,     VDIN0_COM_GCLK_CTRL,  24,   6},
-       {VPU_VIU_VDIN0,     VDIN0_COM_GCLK_CTRL,   4,  18},
-       {VPU_VIU_VDIN0,     VDIN0_COM_GCLK_CTRL,   1,   1},
-       {VPU_VIU_VDIN0,     VDIN0_COM_GCLK_CTRL2,  0,   4},
-       {VPU_VIU_VDIN1,     VDIN1_COM_GCLK_CTRL,  24,   6},
-       {VPU_VIU_VDIN1,     VDIN1_COM_GCLK_CTRL,   4,  18},
-       {VPU_VIU_VDIN1,     VDIN1_COM_GCLK_CTRL,   1,   1},
-       {VPU_VIU_VDIN1,     VDIN1_COM_GCLK_CTRL2,  0,   4},
-       {VPU_DI,            DI_CLKG_CTRL,         26,   3},
-       {VPU_DI,            DI_CLKG_CTRL,         24,   1},
-       {VPU_DI,            DI_CLKG_CTRL,         17,   4},
-       {VPU_DI,            DI_CLKG_CTRL,          0,   2},
-       {VPU_VPP,           VPP_GCLK_CTRL0,       16,  16},
-       {VPU_VPP,           VPP_GCLK_CTRL0,        6,   8},
-       {VPU_VPP,           VPP_GCLK_CTRL0,        2,   2},
-       {VPU_VPP,           VPP_GCLK_CTRL1,        0,  12},
-       {VPU_VPP,           VPP_SC_GCLK_CTRL,     18,   8},
-       {VPU_VPP,           VPP_SC_GCLK_CTRL,      2,  10},
-       {VPU_VPP,           VPP_XVYCC_GCLK_CTRL,   0,  18},
-       {VPU_MAX,           VPU_REG_END,           0,   0},
+       /* vpu module,      reg,                  val, bit, len */
+       {VPU_VPU_TOP,       VPU_CLK_GATE,         1,   1,   1}, /*vpu_sys_clk*/
+       {VPU_VPU_CLKB,      VPU_CLK_GATE,         1,  16,   1},
+       {VPU_RDMA,          VPU_CLK_GATE,         1,  15,   1}, /*rdma_clk*/
+       {VPU_VLOCK,         VPU_CLK_GATE,         1,  14,   1},
+       {VPU_MISC,          VPU_CLK_GATE,         1,   6,   1}, /*hs,vs intr*/
+       {VPU_VENCP,         VPU_CLK_GATE,         1,   3,   1},
+       {VPU_VENCP,         VPU_CLK_GATE,         1,   0,   1},
+       {VPU_VENCL,         VPU_CLK_GATE,         1,   4,   2},
+       {VPU_VENCI,         VPU_CLK_GATE,         1,  10,   2},
+       {VPU_VIU_VDIN0,     VDIN0_COM_GCLK_CTRL,  1,  24,   6},
+       {VPU_VIU_VDIN0,     VDIN0_COM_GCLK_CTRL,  1,   4,  18},
+       {VPU_VIU_VDIN0,     VDIN0_COM_GCLK_CTRL,  1,   1,   1},
+       {VPU_VIU_VDIN0,     VDIN0_COM_GCLK_CTRL2, 1,   0,   4},
+       {VPU_VIU_VDIN1,     VDIN1_COM_GCLK_CTRL,  1,  24,   6},
+       {VPU_VIU_VDIN1,     VDIN1_COM_GCLK_CTRL,  1,   4,  18},
+       {VPU_VIU_VDIN1,     VDIN1_COM_GCLK_CTRL,  1,   1,   1},
+       {VPU_VIU_VDIN1,     VDIN1_COM_GCLK_CTRL2, 1,   0,   4},
+       {VPU_DI,            DI_CLKG_CTRL,         1,  26,   3},
+       {VPU_DI,            DI_CLKG_CTRL,         1,  24,   1},
+       {VPU_DI,            DI_CLKG_CTRL,         1,  17,   4},
+       {VPU_DI,            DI_CLKG_CTRL,         1,   0,   2},
+       {VPU_VPP,           VPP_GCLK_CTRL0,       1,  16,  16},
+       {VPU_VPP,           VPP_GCLK_CTRL0,       1,   6,   8},
+       {VPU_VPP,           VPP_GCLK_CTRL0,       1,   2,   2},
+       {VPU_VPP,           VPP_GCLK_CTRL1,       1,   0,  12},
+       {VPU_VPP,           VPP_SC_GCLK_CTRL,     1,  18,   8},
+       {VPU_VPP,           VPP_SC_GCLK_CTRL,     1,   2,  10},
+       {VPU_VPP,           VPP_XVYCC_GCLK_CTRL,  1,   0,  18},
+       {VPU_MAX,           VPU_REG_END,          0,   0,   0},
 };
 
 static struct vpu_ctrl_s vpu_clk_gate_gxl[] = {
-       /* vpu module,      reg,                  bit,  len */
-       {VPU_VPU_TOP,       VPU_CLK_GATE,          1,   1}, /* vpu_system_clk */
-       {VPU_VPU_CLKB,      VPU_CLK_GATE,         16,   2},
-       {VPU_RDMA,          VPU_CLK_GATE,         15,   1}, /* rdma_clk */
-       {VPU_VLOCK,         VPU_CLK_GATE,         14,   1},
-       {VPU_MISC,          VPU_CLK_GATE,          6,   1}, /* hs,vs interrupt*/
-       {VPU_VENCP,         VPU_CLK_GATE,          3,   1},
-       {VPU_VENCP,         VPU_CLK_GATE,          0,   1},
-       {VPU_VENCL,         VPU_CLK_GATE,          4,   2},
-       {VPU_VENCI,         VPU_CLK_GATE,         10,   2},
-       {VPU_VIU_VDIN0,     VDIN0_COM_GCLK_CTRL,  24,   6},
-       {VPU_VIU_VDIN0,     VDIN0_COM_GCLK_CTRL,   4,  18},
-       {VPU_VIU_VDIN0,     VDIN0_COM_GCLK_CTRL,   1,   1},
-       {VPU_VIU_VDIN0,     VDIN0_COM_GCLK_CTRL2,  0,   4},
-       {VPU_VIU_VDIN1,     VDIN1_COM_GCLK_CTRL,  24,   6},
-       {VPU_VIU_VDIN1,     VDIN1_COM_GCLK_CTRL,   4,  18},
-       {VPU_VIU_VDIN1,     VDIN1_COM_GCLK_CTRL,   1,   1},
-       {VPU_VIU_VDIN1,     VDIN1_COM_GCLK_CTRL2,  0,   4},
-       {VPU_DI,            DI_CLKG_CTRL,         26,   5},
-       {VPU_DI,            DI_CLKG_CTRL,         24,   1},
-       {VPU_DI,            DI_CLKG_CTRL,         17,   5},
-       {VPU_DI,            DI_CLKG_CTRL,          0,   2},
-       {VPU_VPP,           VPP_GCLK_CTRL0,        2,  30},
-       {VPU_VPP,           VPP_GCLK_CTRL1,        0,  12},
-       {VPU_VPP,           VPP_SC_GCLK_CTRL,     18,   8},
-       {VPU_VPP,           VPP_SC_GCLK_CTRL,      2,  10},
-       {VPU_VPP,           VPP_XVYCC_GCLK_CTRL,   0,  18},
-       {VPU_MAX,           VPU_REG_END,           0,   0},
+       /* vpu module,      reg,                  val, bit, len */
+       {VPU_VPU_TOP,       VPU_CLK_GATE,         1,   1,   1}, /*vpu_sys_clk*/
+       {VPU_VPU_CLKB,      VPU_CLK_GATE,         1,  16,   2},
+       {VPU_RDMA,          VPU_CLK_GATE,         1,  15,   1}, /*rdma_clk*/
+       {VPU_VLOCK,         VPU_CLK_GATE,         1,  14,   1},
+       {VPU_MISC,          VPU_CLK_GATE,         1,   6,   1}, /*hs,vs intr*/
+       {VPU_VENCP,         VPU_CLK_GATE,         1,   3,   1},
+       {VPU_VENCP,         VPU_CLK_GATE,         1,   0,   1},
+       {VPU_VENCL,         VPU_CLK_GATE,         1,   4,   2},
+       {VPU_VENCI,         VPU_CLK_GATE,         1,  10,   2},
+       {VPU_VIU_VDIN0,     VDIN0_COM_GCLK_CTRL,  1,  24,   6},
+       {VPU_VIU_VDIN0,     VDIN0_COM_GCLK_CTRL,  1,   4,  18},
+       {VPU_VIU_VDIN0,     VDIN0_COM_GCLK_CTRL,  1,   1,   1},
+       {VPU_VIU_VDIN0,     VDIN0_COM_GCLK_CTRL2, 1,   0,   4},
+       {VPU_VIU_VDIN1,     VDIN1_COM_GCLK_CTRL,  1,  24,   6},
+       {VPU_VIU_VDIN1,     VDIN1_COM_GCLK_CTRL,  1,   4,  18},
+       {VPU_VIU_VDIN1,     VDIN1_COM_GCLK_CTRL,  1,   1,   1},
+       {VPU_VIU_VDIN1,     VDIN1_COM_GCLK_CTRL2, 1,   0,   4},
+       {VPU_DI,            DI_CLKG_CTRL,         1,  26,   5},
+       {VPU_DI,            DI_CLKG_CTRL,         1,  24,   1},
+       {VPU_DI,            DI_CLKG_CTRL,         1,  17,   5},
+       {VPU_DI,            DI_CLKG_CTRL,         1,   0,   2},
+       {VPU_VPP,           VPP_GCLK_CTRL0,       1,   2,  30},
+       {VPU_VPP,           VPP_GCLK_CTRL1,       1,   0,  12},
+       {VPU_VPP,           VPP_SC_GCLK_CTRL,     1,  18,   8},
+       {VPU_VPP,           VPP_SC_GCLK_CTRL,     1,   2,  10},
+       {VPU_VPP,           VPP_XVYCC_GCLK_CTRL,  1,   0,  18},
+       {VPU_MAX,           VPU_REG_END,          0,   0,   0},
 };
 
 static struct vpu_ctrl_s vpu_clk_gate_txl[] = {
-       /* vpu module,      reg,                  bit,  len */
-       {VPU_VPU_TOP,       VPU_CLK_GATE,          1,   1}, /* vpu_system_clk */
-       {VPU_VPU_CLKB,      VPU_CLK_GATE,         16,   1},
-       {VPU_RDMA,          VPU_CLK_GATE,         15,   1}, /* rdma_clk */
-       {VPU_VLOCK,         VPU_CLK_GATE,         14,   1},
-       {VPU_MISC,          VPU_CLK_GATE,          6,   1}, /* hs,vs interrupt*/
-       {VPU_VENCP,         VPU_CLK_GATE,          3,   1},
-       {VPU_VENCP,         VPU_CLK_GATE,          0,   1},
-       {VPU_VENCL,         VPU_CLK_GATE,          4,   2},
-       {VPU_VENCI,         VPU_CLK_GATE,         10,   2},
-       {VPU_VIU_VDIN0,     VDIN0_COM_GCLK_CTRL,  24,   6},
-       {VPU_VIU_VDIN0,     VDIN0_COM_GCLK_CTRL,   4,  18},
-       {VPU_VIU_VDIN0,     VDIN0_COM_GCLK_CTRL,   1,   1},
-       {VPU_VIU_VDIN0,     VDIN0_COM_GCLK_CTRL2,  0,   4},
-       {VPU_VIU_VDIN1,     VDIN1_COM_GCLK_CTRL,  24,   6},
-       {VPU_VIU_VDIN1,     VDIN1_COM_GCLK_CTRL,   4,  18},
-       {VPU_VIU_VDIN1,     VDIN1_COM_GCLK_CTRL,   1,   1},
-       {VPU_VIU_VDIN1,     VDIN1_COM_GCLK_CTRL2,  0,   4},
-       {VPU_DI,            DI_CLKG_CTRL,         26,   5},
-       {VPU_DI,            DI_CLKG_CTRL,         24,   1},
-       {VPU_DI,            DI_CLKG_CTRL,         17,   5},
-       {VPU_DI,            DI_CLKG_CTRL,          0,   2},
-       {VPU_VPP,           VPP_GCLK_CTRL0,        2,  30},
-       {VPU_VPP,           VPP_GCLK_CTRL1,        0,  12},
-       {VPU_VPP,           VPP_SC_GCLK_CTRL,     18,   8},
-       {VPU_VPP,           VPP_SC_GCLK_CTRL,      2,  10},
-       {VPU_VPP,           VPP_XVYCC_GCLK_CTRL,   0,  18},
-       {VPU_MAX,           VPU_REG_END,           0,   0},
+       /* vpu module,      reg,                  val, bit, len */
+       {VPU_VPU_TOP,       VPU_CLK_GATE,         1,   1,   1}, /*vpu_sys_clk*/
+       {VPU_VPU_CLKB,      VPU_CLK_GATE,         1,  16,   1},
+       {VPU_RDMA,          VPU_CLK_GATE,         1,  15,   1}, /*rdma_clk*/
+       {VPU_VLOCK,         VPU_CLK_GATE,         1,  14,   1},
+       {VPU_MISC,          VPU_CLK_GATE,         1,   6,   1}, /*hs,vs intr*/
+       {VPU_VENCP,         VPU_CLK_GATE,         1,   3,   1},
+       {VPU_VENCP,         VPU_CLK_GATE,         1,   0,   1},
+       {VPU_VENCL,         VPU_CLK_GATE,         1,   4,   2},
+       {VPU_VENCI,         VPU_CLK_GATE,         1,  10,   2},
+       {VPU_VIU_VDIN0,     VDIN0_COM_GCLK_CTRL,  1,  24,   6},
+       {VPU_VIU_VDIN0,     VDIN0_COM_GCLK_CTRL,  1,   4,  18},
+       {VPU_VIU_VDIN0,     VDIN0_COM_GCLK_CTRL,  1,   1,   1},
+       {VPU_VIU_VDIN0,     VDIN0_COM_GCLK_CTRL2, 1,   0,   4},
+       {VPU_VIU_VDIN1,     VDIN1_COM_GCLK_CTRL,  1,  24,   6},
+       {VPU_VIU_VDIN1,     VDIN1_COM_GCLK_CTRL,  1,   4,  18},
+       {VPU_VIU_VDIN1,     VDIN1_COM_GCLK_CTRL,  1,   1,   1},
+       {VPU_VIU_VDIN1,     VDIN1_COM_GCLK_CTRL2, 1,   0,   4},
+       {VPU_DI,            DI_CLKG_CTRL,         1,  26,   5},
+       {VPU_DI,            DI_CLKG_CTRL,         1,  24,   1},
+       {VPU_DI,            DI_CLKG_CTRL,         1,  17,   5},
+       {VPU_DI,            DI_CLKG_CTRL,         1,   0,   2},
+       {VPU_VPP,           VPP_GCLK_CTRL0,       1,   2,  30},
+       {VPU_VPP,           VPP_GCLK_CTRL1,       1,   0,  12},
+       {VPU_VPP,           VPP_SC_GCLK_CTRL,     1,  18,   8},
+       {VPU_VPP,           VPP_SC_GCLK_CTRL,     1,   2,  10},
+       {VPU_VPP,           VPP_XVYCC_GCLK_CTRL,  1,   0,  18},
+       {VPU_MAX,           VPU_REG_END,          0,   0,   0},
 };
 
 static struct vpu_ctrl_s vpu_clk_gate_txlx[] = {
-       /* vpu module,      reg,                  bit,  len */
-       {VPU_VPU_TOP,       VPU_CLK_GATE,          1,   1}, /* vpu_system_clk */
-       {VPU_VPU_CLKB,      VPU_CLK_GATE,         16,   1},
-       {VPU_RDMA,          VPU_CLK_GATE,         15,   1}, /* rdma_clk */
-       {VPU_VLOCK,         VPU_CLK_GATE,         14,   1},
-       {VPU_MISC,          VPU_CLK_GATE,          6,   1}, /* hs,vs interrupt*/
-       {VPU_VENCP,         VPU_CLK_GATE,          3,   1},
-       {VPU_VENCP,         VPU_CLK_GATE,          0,   1},
-       {VPU_VENCL,         VPU_CLK_GATE,          4,   2},
-       {VPU_VENCI,         VPU_CLK_GATE,         10,   2},
-       {VPU_VIU_VDIN0,     VDIN0_COM_GCLK_CTRL,  24,   6},
-       {VPU_VIU_VDIN0,     VDIN0_COM_GCLK_CTRL,   4,  18},
-       {VPU_VIU_VDIN0,     VDIN0_COM_GCLK_CTRL,   1,   1},
-       {VPU_VIU_VDIN0,     VDIN0_COM_GCLK_CTRL2,  0,   4},
-       {VPU_VIU_VDIN1,     VDIN1_COM_GCLK_CTRL,  24,   6},
-       {VPU_VIU_VDIN1,     VDIN1_COM_GCLK_CTRL,   4,  18},
-       {VPU_VIU_VDIN1,     VDIN1_COM_GCLK_CTRL,   1,   1},
-       {VPU_VIU_VDIN1,     VDIN1_COM_GCLK_CTRL2,  0,   4},
-       {VPU_VPP,           VPP_GCLK_CTRL0,        2,  30},
-       {VPU_VPP,           VPP_GCLK_CTRL1,        0,  12},
-       {VPU_VPP,           VPP_SC_GCLK_CTRL,     18,   8},
-       {VPU_VPP,           VPP_SC_GCLK_CTRL,      2,  10},
-       {VPU_VPP,           VPP_XVYCC_GCLK_CTRL,   0,  18},
-       {VPU_MAX,           VPU_REG_END,           0,   0},
+       /* vpu module,      reg,                  val, bit, len */
+       {VPU_VPU_TOP,       VPU_CLK_GATE,         1,   1,   1}, /*vpu_sys_clk*/
+       {VPU_VPU_CLKB,      VPU_CLK_GATE,         1,  16,   1},
+       {VPU_RDMA,          VPU_CLK_GATE,         1,  15,   1}, /*rdma_clk*/
+       {VPU_VLOCK,         VPU_CLK_GATE,         1,  14,   1},
+       {VPU_MISC,          VPU_CLK_GATE,         1,   6,   1}, /*hs,vs intr*/
+       {VPU_VENCP,         VPU_CLK_GATE,         1,   3,   1},
+       {VPU_VENCP,         VPU_CLK_GATE,         1,   0,   1},
+       {VPU_VENCL,         VPU_CLK_GATE,         1,   4,   2},
+       {VPU_VENCI,         VPU_CLK_GATE,         1,  10,   2},
+       {VPU_VIU_VDIN0,     VDIN0_COM_GCLK_CTRL,  1,  24,   6},
+       {VPU_VIU_VDIN0,     VDIN0_COM_GCLK_CTRL,  1,   4,  18},
+       {VPU_VIU_VDIN0,     VDIN0_COM_GCLK_CTRL,  1,   1,   1},
+       {VPU_VIU_VDIN0,     VDIN0_COM_GCLK_CTRL2, 1,   0,   4},
+       {VPU_VIU_VDIN1,     VDIN1_COM_GCLK_CTRL,  1,  24,   6},
+       {VPU_VIU_VDIN1,     VDIN1_COM_GCLK_CTRL,  1,   4,  18},
+       {VPU_VIU_VDIN1,     VDIN1_COM_GCLK_CTRL,  1,   1,   1},
+       {VPU_VIU_VDIN1,     VDIN1_COM_GCLK_CTRL2, 1,   0,   4},
+       {VPU_VPP,           VPP_GCLK_CTRL0,       1,   2,  30},
+       {VPU_VPP,           VPP_GCLK_CTRL1,       1,   0,  12},
+       {VPU_VPP,           VPP_SC_GCLK_CTRL,     1,  18,   8},
+       {VPU_VPP,           VPP_SC_GCLK_CTRL,     1,   2,  10},
+       {VPU_VPP,           VPP_XVYCC_GCLK_CTRL,  1,   0,  18},
+       {VPU_MAX,           VPU_REG_END,          0,   0,   0},
 };
 
 static struct vpu_ctrl_s vpu_clk_gate_axg[] = {
-       /* vpu module,      reg,                   bit,  len */
-       {VPU_VPU_TOP,       VPU_CLK_GATE,          1,   1},
-       {VPU_VLOCK,         VPU_CLK_GATE,         14,   1},
-       {VPU_MISC,          VPU_CLK_GATE,          6,   1},
-       {VPU_VENCL,         VPU_CLK_GATE,          4,   2},
-       {VPU_VPP,           VPP_GCLK_CTRL0,       16,  16},
-       {VPU_VPP,           VPP_GCLK_CTRL0,        6,   8},
-       {VPU_VPP,           VPP_GCLK_CTRL0,        2,   2},
-       {VPU_VPP,           VPP_GCLK_CTRL1,        0,  12},
-       {VPU_VPP,           VPP_SC_GCLK_CTRL,     18,   8},
-       {VPU_VPP,           VPP_SC_GCLK_CTRL,      2,  10},
-       {VPU_VPP,           VPP_XVYCC_GCLK_CTRL,   0,  18},
-       {VPU_MAX,           VPU_REG_END,           0,   0},
+       /* vpu module,      reg,                  val, bit, len */
+       {VPU_VPU_TOP,       VPU_CLK_GATE,         1,   1,   1},
+       {VPU_VLOCK,         VPU_CLK_GATE,         1,  14,   1},
+       {VPU_MISC,          VPU_CLK_GATE,         1,   6,   1},
+       {VPU_VENCL,         VPU_CLK_GATE,         1,   4,   2},
+       {VPU_VPP,           VPP_GCLK_CTRL0,       1,  16,  16},
+       {VPU_VPP,           VPP_GCLK_CTRL0,       1,   6,   8},
+       {VPU_VPP,           VPP_GCLK_CTRL0,       1,   2,   2},
+       {VPU_VPP,           VPP_GCLK_CTRL1,       1,   0,  12},
+       {VPU_VPP,           VPP_SC_GCLK_CTRL,     1,  18,   8},
+       {VPU_VPP,           VPP_SC_GCLK_CTRL,     1,   2,  10},
+       {VPU_VPP,           VPP_XVYCC_GCLK_CTRL,  1,   0,  18},
+       {VPU_MAX,           VPU_REG_END,          0,   0,   0},
 };
 
 static struct vpu_ctrl_s vpu_clk_gate_g12a[] = {
-       /* vpu module,      reg,                  bit,  len */
-       {VPU_VPU_TOP,       VPU_CLK_GATE,          1,   1}, /* vpu_system_clk */
-       {VPU_VPU_CLKB,      VPU_CLK_GATE,         18,   1},
-       {VPU_CLK_B_REG_LATCH, VPU_CLK_GATE,       17,   1},
-       {VPU_CLK_VIB,       VPU_CLK_GATE,         16,   1},
-       {VPU_RDMA,          VPU_CLK_GATE,         15,   1}, /* rdma_clk */
-       {VPU_VLOCK,         VPU_CLK_GATE,         14,   1},
-       {VPU_MISC,          VPU_CLK_GATE,          6,   1}, /* hs,vs interrupt*/
-       {VPU_VENCP,         VPU_CLK_GATE,          3,   1},
-       {VPU_VENCP,         VPU_CLK_GATE,          0,   1},
-       {VPU_VENCL,         VPU_CLK_GATE,          4,   2},
-       {VPU_VENCI,         VPU_CLK_GATE,         10,   2},
-       {VPU_VIU_VDIN0,     VDIN0_COM_GCLK_CTRL,  24,   6},
-       {VPU_VIU_VDIN0,     VDIN0_COM_GCLK_CTRL,   4,  18},
-       {VPU_VIU_VDIN0,     VDIN0_COM_GCLK_CTRL,   1,   1},
-       {VPU_VIU_VDIN0,     VDIN0_COM_GCLK_CTRL2,  0,   4},
-       {VPU_VIU_VDIN1,     VDIN1_COM_GCLK_CTRL,  24,   6},
-       {VPU_VIU_VDIN1,     VDIN1_COM_GCLK_CTRL,   4,  18},
-       {VPU_VIU_VDIN1,     VDIN1_COM_GCLK_CTRL,   1,   1},
-       {VPU_VIU_VDIN1,     VDIN1_COM_GCLK_CTRL2,  0,   4},
-       {VPU_DI,            DI_CLKG_CTRL,         26,   5},
-       {VPU_DI,            DI_CLKG_CTRL,         24,   1},
-       {VPU_DI,            DI_CLKG_CTRL,         17,   5},
-       {VPU_DI,            DI_CLKG_CTRL,          0,   2},
-       {VPU_VPP,           VPP_GCLK_CTRL0,        2,  30},
-       {VPU_VPP,           VPP_GCLK_CTRL1,        0,  12},
-       {VPU_VPP,           VPP_SC_GCLK_CTRL,     18,   8},
-       {VPU_VPP,           VPP_SC_GCLK_CTRL,      2,  10},
-       {VPU_VPP,           VPP_XVYCC_GCLK_CTRL,   0,  18},
-       {VPU_MAX,           VPU_REG_END,           0,   0},
+       /* vpu module,      reg,                  val, bit, len */
+       {VPU_VPU_TOP,       VPU_CLK_GATE,         1,   1,   1}, /*vpu_sys_clk*/
+       {VPU_VPU_CLKB,      VPU_CLK_GATE,         1,  18,   1},
+       {VPU_CLK_B_REG_LATCH, VPU_CLK_GATE,       1,  17,   1},
+       {VPU_CLK_VIB,       VPU_CLK_GATE,         1,  16,   1},
+       {VPU_RDMA,          VPU_CLK_GATE,         1,  15,   1}, /*rdma_clk*/
+       {VPU_VLOCK,         VPU_CLK_GATE,         1,  14,   1},
+       {VPU_MISC,          VPU_CLK_GATE,         1,   6,   1}, /*hs,vs intr*/
+       {VPU_VENCP,         VPU_CLK_GATE,         1,   3,   1},
+       {VPU_VENCP,         VPU_CLK_GATE,         1,   0,   1},
+       {VPU_VENCL,         VPU_CLK_GATE,         1,   4,   2},
+       {VPU_VENCI,         VPU_CLK_GATE,         1,  10,   2},
+       {VPU_VIU_VDIN0,     VDIN0_COM_GCLK_CTRL,  1,  24,   6},
+       {VPU_VIU_VDIN0,     VDIN0_COM_GCLK_CTRL,  1,   4,  18},
+       {VPU_VIU_VDIN0,     VDIN0_COM_GCLK_CTRL,  1,   1,   1},
+       {VPU_VIU_VDIN0,     VDIN0_COM_GCLK_CTRL2, 1,   0,   4},
+       {VPU_VIU_VDIN1,     VDIN1_COM_GCLK_CTRL,  1,  24,   6},
+       {VPU_VIU_VDIN1,     VDIN1_COM_GCLK_CTRL,  1,   4,  18},
+       {VPU_VIU_VDIN1,     VDIN1_COM_GCLK_CTRL,  1,   1,   1},
+       {VPU_VIU_VDIN1,     VDIN1_COM_GCLK_CTRL2, 1,   0,   4},
+       {VPU_DI,            DI_CLKG_CTRL,         1,  26,   5},
+       {VPU_DI,            DI_CLKG_CTRL,         1,  24,   1},
+       {VPU_DI,            DI_CLKG_CTRL,         1,  17,   5},
+       {VPU_DI,            DI_CLKG_CTRL,         1,   0,   2},
+       {VPU_VPP,           VPP_GCLK_CTRL0,       1,   2,  30},
+       {VPU_VPP,           VPP_GCLK_CTRL1,       1,   0,  12},
+       {VPU_VPP,           VPP_SC_GCLK_CTRL,     1,  18,   8},
+       {VPU_VPP,           VPP_SC_GCLK_CTRL,     1,   2,  10},
+       {VPU_VPP,           VPP_XVYCC_GCLK_CTRL,  1,   0,  18},
+       {VPU_MAX,           VPU_REG_END,          0,   0,   0},
+};
+
+/* ******************************************************* */
+/*                 VPU module init table                 */
+/* ******************************************************* */
+static struct vpu_ctrl_s vpu_module_init_gxm[] = {
+       /* 0, reg,                       val,        bit, len */
+       {0,   DOLBY_CORE1_CLKGATE_CTRL,  0x55555555, 0,   32},
+       {0,   DOLBY_CORE2A_CLKGATE_CTRL, 0x55555555, 0,   32},
+       {0,   DOLBY_CORE3_CLKGATE_CTRL,  0x55555555, 0,   32},
+       {0,   VPU_REG_END,               0,          0,   0},
+};
+
+static struct vpu_ctrl_s vpu_module_init_txlx[] = {
+       /* 0, reg,                       val, bit, len */
+       {0,   DOLBY_TV_CLKGATE_CTRL,     1,   10,  2},
+       {0,   DOLBY_TV_CLKGATE_CTRL,     1,   2,   2},
+       {0,   DOLBY_TV_CLKGATE_CTRL,     1,   4,   2},
+       {0,   DOLBY_CORE2A_CLKGATE_CTRL, 1,   10,  2},
+       {0,   DOLBY_CORE2A_CLKGATE_CTRL, 1,   2,   2},
+       {0,   DOLBY_CORE2A_CLKGATE_CTRL, 1,   4,   2},
+       {0,   DOLBY_CORE3_CLKGATE_CTRL,  0,   1,   1},
+       {0,   DOLBY_CORE3_CLKGATE_CTRL,  1,   2,   2},
+       {0,   VPU_REG_END,               0,   0,   0},
+};
+
+/* ******************************************************* */
+/*                 VPU reset table                    */
+/* ******************************************************* */
+static struct vpu_reset_s vpu_reset_gx[] = {
+       /* reg,             mask */
+       {RESET0_LEVEL,      ((1<<5) | (1<<10) | (1<<19) | (1<<13))},
+       {RESET1_LEVEL,      (1<<5)},
+       {RESET2_LEVEL,      (1<<15)},
+       {RESET4_LEVEL,      ((1<<6) | (1<<7) | (1<<13) | (1<<5) |
+                               (1<<9) | (1<<4) | (1<<12))},
+       {RESET7_LEVEL,      (1<<7)},
+       {VPU_REG_END,       0},
+};
+
+static struct vpu_reset_s vpu_reset_txlx[] = {
+       /* reg,             mask */
+       {RESET0_LEVEL_TXLX, ((1<<5) | (1<<10) | (1<<19) | (1<<13))},
+       {RESET1_LEVEL_TXLX, (1<<5)},
+       {RESET2_LEVEL_TXLX, (1<<15)},
+       {RESET3_LEVEL_TXLX, ((1<<6) | (1<<7) | (1<<13) | (1<<5) |
+                               (1<<9) | (1<<4) | (1<<12))},
+       {RESET7_LEVEL_TXLX, (1<<7)},
+       {VPU_REG_END,       0},
+};
+
+static struct vpu_reset_s vpu_reset_tl1[] = {
+       /* reg,             mask */
+       {RESET0_LEVEL_TXLX, ((1<<5) | (1<<10) | (1<<19) | (1<<13))},
+       {RESET1_LEVEL_TXLX, ((1<<5) | (1<<4))},
+       {RESET2_LEVEL_TXLX, (1<<15)},
+       {RESET4_LEVEL_TXLX, ((1<<6) | (1<<7) | (1<<13) | (1<<5) |
+                               (1<<9) | (1<<4) | (1<<12))},
+       {RESET7_LEVEL_TXLX, (1<<7)},
+       {VPU_REG_END,       0},
 };
 
-/* ************************************************ */
 
 #endif

diff --git a/drivers/amlogic/media/common/vpu/vpu_module.h b/drivers/amlogic/media/common/vpu/vpu_module.h
index 85f6efd..30f0cd9 100644 (file)
--- a/drivers/amlogic/media/common/vpu/vpu_module.h
+++ b/drivers/amlogic/media/common/vpu/vpu_module.h
@@ -59,6 +59,7 @@ static char *vpu_mod_table[] = {
        "vencp",
        "vencl",
        "venci",
+       "ls_stts",
        "ldim_stts",
        "tv_decoder_cvd2",
        "xvycc_lut",
@@ -73,10 +74,16 @@ static char *vpu_mod_table[] = {
        "osd_bld34",
        "prime_dolby_ram",
        "vd2_ofifo",
+       "ds",
        "lut3d",
        "viu2_osd_rotation",
+       "vi_dipre",
        "rdma",
 
+       "axi_wr1",
+       "axi_wr0",
+       "afbce",
+
        "vpu_mod_max",
 
        /* for clk_gate */

diff --git a/drivers/amlogic/media/common/vpu/vpu_power_init.c b/drivers/amlogic/media/common/vpu/vpu_power_init.c
index c59aa6c..07c5c84 100644 (file)
--- a/drivers/amlogic/media/common/vpu/vpu_power_init.c
+++ b/drivers/amlogic/media/common/vpu/vpu_power_init.c
@@ -18,15 +18,9 @@
 #include <linux/init.h>
 #include <linux/module.h>
 #include <linux/platform_device.h>
-#include <linux/io.h>
 #include <linux/slab.h>
 #include <linux/err.h>
-#include <linux/of.h>
-#include <linux/of_device.h>
 #include <linux/delay.h>
-#include <linux/clk.h>
-#include <linux/clk-provider.h>
-#include <linux/amlogic/cpu_version.h>
 #include <linux/amlogic/media/vpu/vpu.h>
 #include "vpu_reg.h"
 #include "vpu.h"
@@ -38,41 +32,30 @@ void vpu_mem_pd_init_off(void)
        VPUPR("%s\n", __func__);
 }
 
-void vpu_clk_gate_init_off(void)
+void vpu_module_init_config(void)
 {
+       struct vpu_ctrl_s *ctrl_table;
+       unsigned int _reg, _val, _bit, _len;
+       int i = 0, cnt;
+
        VPUPR("%s\n", __func__);
 
-       switch (vpu_conf.data->chip_type) {
-       case VPU_CHIP_TXLX:
-               /* dolby core1 */
-               vpu_vcbus_setb(DOLBY_TV_CLKGATE_CTRL, 1, 10, 2);
-               vpu_vcbus_setb(DOLBY_TV_CLKGATE_CTRL, 1, 2, 2);
-               vpu_vcbus_setb(DOLBY_TV_CLKGATE_CTRL, 1, 4, 2);
-               /* dolby core2 */
-               vpu_vcbus_setb(DOLBY_CORE2A_CLKGATE_CTRL, 1, 10, 2);
-               vpu_vcbus_setb(DOLBY_CORE2A_CLKGATE_CTRL, 1, 2, 2);
-               vpu_vcbus_setb(DOLBY_CORE2A_CLKGATE_CTRL, 1, 4, 2);
-               /* dolby core3 */
-               vpu_vcbus_setb(DOLBY_CORE3_CLKGATE_CTRL, 0, 1, 1);
-               vpu_vcbus_setb(DOLBY_CORE3_CLKGATE_CTRL, 1, 2, 2);
-               break;
-       case VPU_CHIP_GXM:
-               vpu_vcbus_write(DOLBY_CORE1_CLKGATE_CTRL, 0x55555555);
-               vpu_vcbus_write(DOLBY_CORE2A_CLKGATE_CTRL, 0x55555555);
-               vpu_vcbus_write(DOLBY_CORE3_CLKGATE_CTRL, 0x55555555);
-               break;
-       default:
-               break;
+       /* vpu clk gate init off */
+       cnt = vpu_conf.data->module_init_table_cnt;
+       ctrl_table = vpu_conf.data->module_init_table;
+       if (ctrl_table) {
+               while (i < cnt) {
+                       if (ctrl_table[i].reg == VPU_REG_END)
+                               break;
+                       _reg = ctrl_table[i].reg;
+                       _val = ctrl_table[i].val;
+                       _bit = ctrl_table[i].bit;
+                       _len = ctrl_table[i].len;
+                       vpu_vcbus_setb(_reg, _val, _bit, _len);
+                       i++;
+               }
        }
 
-       if (vpu_debug_print_flag)
-               VPUPR("%s finish\n", __func__);
-}
-
-void vpu_module_init_config(void)
-{
-       VPUPR("%s\n", __func__);
-
        /* dmc_arb_config */
        vpu_vcbus_write(VPU_RDARB_MODE_L1C1, 0x210000);
        vpu_vcbus_write(VPU_RDARB_MODE_L1C2, 0x10000);
@@ -83,10 +66,11 @@ void vpu_module_init_config(void)
                VPUPR("%s finish\n", __func__);
 }
 
-void vpu_power_on_gx(void)
+void vpu_power_on(void)
 {
-       struct vpu_ctrl_s *table;
-       unsigned int _reg, _bit, _len;
+       struct vpu_ctrl_s *ctrl_table;
+       struct vpu_reset_s *reset_table;
+       unsigned int _reg, _bit, _len, mask;
        int i = 0, cnt;
 
        VPUPR("vpu_power_on\n");
@@ -96,13 +80,13 @@ void vpu_power_on_gx(void)
 
        /* power up memories */
        cnt = vpu_conf.data->mem_pd_table_cnt;
-       table = vpu_conf.data->mem_pd_table;
+       ctrl_table = vpu_conf.data->mem_pd_table;
        while (i < cnt) {
-               if (table[i].vmod == VPU_MOD_MAX)
+               if (ctrl_table[i].vmod == VPU_MOD_MAX)
                        break;
-               _reg = table[i].reg;
-               _bit = table[i].bit;
-               _len = table[i].len;
+               _reg = ctrl_table[i].reg;
+               _bit = ctrl_table[i].bit;
+               _len = ctrl_table[i].len;
                vpu_hiu_setb(_reg, 0x0, _bit, _len);
                udelay(5);
                i++;
@@ -116,132 +100,39 @@ void vpu_power_on_gx(void)
        /* Reset VIU + VENC */
        /* Reset VENCI + VENCP + VADC + VENCL */
        /* Reset HDMI-APB + HDMI-SYS + HDMI-TX + HDMI-CEC */
-       vpu_cbus_clr_mask(RESET0_LEVEL, ((1<<5) | (1<<10) | (1<<19) | (1<<13)));
-       vpu_cbus_clr_mask(RESET1_LEVEL, (1<<5));
-       vpu_cbus_clr_mask(RESET2_LEVEL, (1<<15));
-       vpu_cbus_clr_mask(RESET4_LEVEL, ((1<<6) | (1<<7) | (1<<13) | (1<<5) |
-                                       (1<<9) | (1<<4) | (1<<12)));
-       vpu_cbus_clr_mask(RESET7_LEVEL, (1<<7));
-
-       /* Remove VPU_HDMI ISO */
-       vpu_ao_setb(AO_RTI_GEN_PWR_SLEEP0, 0, 9, 1); /* [9] VPU_HDMI */
-
-       /* release Reset */
-       vpu_cbus_set_mask(RESET0_LEVEL, ((1 << 5) | (1<<10) | (1<<19) |
-                                       (1<<13)));
-       vpu_cbus_set_mask(RESET1_LEVEL, (1<<5));
-       vpu_cbus_set_mask(RESET2_LEVEL, (1<<15));
-       vpu_cbus_set_mask(RESET4_LEVEL, ((1<<6) | (1<<7) | (1<<13) | (1<<5) |
-                                       (1<<9) | (1<<4) | (1<<12)));
-       vpu_cbus_set_mask(RESET7_LEVEL, (1<<7));
-
-       if (vpu_debug_print_flag)
-               VPUPR("%s finish\n", __func__);
-}
-
-void vpu_power_off_gx(void)
-{
-       struct vpu_ctrl_s *table;
-       unsigned int _reg, _bit, _len;
-       int i = 0, cnt;
-
-       VPUPR("vpu_power_off\n");
-
-       /* Power down VPU_HDMI */
-       /* Enable Isolation */
-       vpu_ao_setb(AO_RTI_GEN_PWR_SLEEP0, 1, 9, 1); /* ISO */
-       udelay(20);
-
-       /* power down memories */
-       cnt = vpu_conf.data->mem_pd_table_cnt;
-       table = vpu_conf.data->mem_pd_table;
-       while (i < cnt) {
-               if (table[i].vmod == VPU_MOD_MAX)
+       reset_table = vpu_conf.data->reset_table;
+       i = 0;
+       while (i < VPU_RESET_CNT_MAX) {
+               if (reset_table[i].reg == VPU_REG_END)
                        break;
-               _reg = table[i].reg;
-               _bit = table[i].bit;
-               _len = table[i].len;
-               vpu_hiu_setb(_reg, 0x3, _bit, _len);
-               udelay(5);
+               _reg = reset_table[i].reg;
+               mask = reset_table[i].mask;
+               vpu_cbus_clr_mask(_reg, mask);
                i++;
        }
-       for (i = 8; i < 16; i++) {
-               vpu_hiu_setb(HHI_MEM_PD_REG0, 0x1, i, 1);
-               udelay(5);
-       }
-       udelay(20);
-
-       /* Power down VPU domain */
-       vpu_ao_setb(AO_RTI_GEN_PWR_SLEEP0, 1, 8, 1); /* PDN */
-
-       vpu_hiu_setb(HHI_VAPBCLK_CNTL, 0, 8, 1);
-       vpu_hiu_setb(HHI_VPU_CLK_CNTL, 0, 8, 1);
-
-       if (vpu_debug_print_flag)
-               VPUPR("%s finish\n", __func__);
-}
-
-void vpu_power_on_txlx(void)
-{
-       struct vpu_ctrl_s *table;
-       unsigned int _reg, _bit, _len;
-       int i = 0, cnt;
-
-       VPUPR("vpu_power_on\n");
-
-       vpu_ao_setb(AO_RTI_GEN_PWR_SLEEP0, 0, 8, 1); /* [8] power on */
-       udelay(20);
-
-       /* power up memories */
-       cnt = vpu_conf.data->mem_pd_table_cnt;
-       table = vpu_conf.data->mem_pd_table;
-       while (i < cnt) {
-               if (table[i].vmod == VPU_MOD_MAX)
+       udelay(5);
+       /* release Reset */
+       i = 0;
+       while (i < VPU_RESET_CNT_MAX) {
+               if (reset_table[i].reg == VPU_REG_END)
                        break;
-               _reg = table[i].reg;
-               _bit = table[i].bit;
-               _len = table[i].len;
-               vpu_hiu_setb(_reg, 0x0, _bit, _len);
-               udelay(5);
+               _reg = reset_table[i].reg;
+               mask = reset_table[i].mask;
+               vpu_cbus_set_mask(_reg, mask);
                i++;
        }
-       for (i = 8; i < 16; i++) {
-               vpu_hiu_setb(HHI_MEM_PD_REG0, 0, i, 1);
-               udelay(5);
-       }
-       udelay(20);
-
-       /* Reset VIU + VENC */
-       /* Reset VENCI + VENCP + VADC + VENCL */
-       /* Reset HDMI-APB + HDMI-SYS + HDMI-TX + HDMI-CEC */
-       vpu_cbus_clr_mask(RESET0_LEVEL_TXLX, ((1<<5) | (1<<10) | (1<<19) |
-                                       (1<<13)));
-       vpu_cbus_clr_mask(RESET1_LEVEL_TXLX, (1<<5));
-       vpu_cbus_clr_mask(RESET2_LEVEL_TXLX, (1<<15));
-       vpu_cbus_clr_mask(RESET4_LEVEL_TXLX, ((1<<6) | (1<<7) | (1<<13) |
-                                       (1<<5) | (1<<9) | (1<<4) | (1<<12)));
-       vpu_cbus_clr_mask(RESET7_LEVEL_TXLX, (1<<7));
 
        /* Remove VPU_HDMI ISO */
        vpu_ao_setb(AO_RTI_GEN_PWR_SLEEP0, 0, 9, 1); /* [9] VPU_HDMI */
 
-       /* release Reset */
-       vpu_cbus_set_mask(RESET0_LEVEL_TXLX, ((1 << 5) | (1<<10) | (1<<19) |
-                                       (1<<13)));
-       vpu_cbus_set_mask(RESET1_LEVEL_TXLX, (1<<5));
-       vpu_cbus_set_mask(RESET2_LEVEL_TXLX, (1<<15));
-       vpu_cbus_set_mask(RESET4_LEVEL_TXLX, ((1<<6) | (1<<7) | (1<<13) |
-                                       (1<<5) | (1<<9) | (1<<4) | (1<<12)));
-       vpu_cbus_set_mask(RESET7_LEVEL_TXLX, (1<<7));
-
        if (vpu_debug_print_flag)
                VPUPR("%s finish\n", __func__);
 }
 
-void vpu_power_off_txlx(void)
+void vpu_power_off(void)
 {
-       struct vpu_ctrl_s *table;
-       unsigned int _reg, _bit, _len;
+       struct vpu_ctrl_s *ctrl_table;
+       unsigned int _val, _reg, _bit, _len;
        int i = 0, cnt;
 
        VPUPR("vpu_power_off\n");
@@ -253,14 +144,18 @@ void vpu_power_off_txlx(void)
 
        /* power down memories */
        cnt = vpu_conf.data->mem_pd_table_cnt;
-       table = vpu_conf.data->mem_pd_table;
+       ctrl_table = vpu_conf.data->mem_pd_table;
        while (i < cnt) {
-               if (table[i].vmod == VPU_MOD_MAX)
+               if (ctrl_table[i].vmod == VPU_MOD_MAX)
                        break;
-               _reg = table[i].reg;
-               _bit = table[i].bit;
-               _len = table[i].len;
-               vpu_hiu_setb(_reg, 0x3, _bit, _len);
+               _reg = ctrl_table[i].reg;
+               _bit = ctrl_table[i].bit;
+               _len = ctrl_table[i].len;
+               if (_len == 32)
+                       _val = 0xffffffff;
+               else
+                       _val = (1 << _len) - 1;
+               vpu_hiu_setb(_reg, _val, _bit, _len);
                udelay(5);
                i++;
        }

diff --git a/drivers/amlogic/media/common/vpu/vpu_reg.h b/drivers/amlogic/media/common/vpu/vpu_reg.h
index 7fb946e..4bac30b 100644 (file)
--- a/drivers/amlogic/media/common/vpu/vpu_reg.h
+++ b/drivers/amlogic/media/common/vpu/vpu_reg.h
@@ -40,6 +40,8 @@
 #define HHI_VPU_MEM_PD_REG0          0x41
 #define HHI_VPU_MEM_PD_REG1          0x42
 #define HHI_VPU_MEM_PD_REG2          0x4d
+#define HHI_VPU_MEM_PD_REG3          0x4e
+#define HHI_VPU_MEM_PD_REG4          0x4c
 
 #define HHI_VPU_CLKC_CNTL            0x6d
 #define HHI_VPU_CLK_CNTL             0x6f

diff --git a/include/linux/amlogic/media/vpu/vpu.h b/include/linux/amlogic/media/vpu/vpu.h
index dac73ee..674b44b 100644 (file)
--- a/include/linux/amlogic/media/vpu/vpu.h
+++ b/include/linux/amlogic/media/vpu/vpu.h
@@ -59,13 +59,14 @@ enum vpu_mod_e {
        VPU_VENCP,            /* reg1[21:20] //common */
        VPU_VENCL,            /* reg1[23:22] //common */
        VPU_VENCI,            /* reg1[25:24] //common */
+       VPU_LS_STTS,          /* reg1[27:26] //tl1 */
        VPU_LDIM_STTS,        /* reg1[29:28] //GXTVBB, GXL, TXL, TXLX */
        VPU_TV_DEC_CVD2,      /* reg1[29:28] */
        VPU_XVYCC_LUT,        /* reg1[31:30] //GXTVBB, GXL, TXL, TXLX */
        VPU_VD2_OSD2_SCALE,   /* reg1[31:30] //G12A */
 
        VPU_VIU_WM,           /* reg2[1:0]   //GXL, TXL, TXLX */
-       VPU_TCON,             /* reg2[3:2]   //TXHD */
+       VPU_TCON,             /* reg2[3:2]   //TXHD, TL1 */
        VPU_VIU_OSD3,         /* reg2[5:4]   //G12A */
        VPU_VIU_OSD4,         /* reg2[7:6]   //G12A */
        VPU_MAIL_AFBCD,       /* reg2[9:8]   //G12A */
@@ -73,10 +74,16 @@ enum vpu_mod_e {
        VPU_OSD_BLD34,        /* reg2[13:12] //G12A */
        VPU_PRIME_DOLBY_RAM,  /* reg2[15:14] //G12A */
        VPU_VD2_OFIFO,        /* reg2[17:16] //G12A */
+       VPU_DS,               /* reg2[19:18] //TL1 */
        VPU_LUT3D,            /* reg2[21:20] //G12B */
        VPU_VIU2_OSD_ROT,     /* reg2[23:22] //G12B */
+       VPU_VI_DIPRE,         /* reg2[27:24] //TL1 */
        VPU_RDMA,             /* reg2[31:30] //G12A */
 
+       VPU_AXI_WR1,          /* reg4[1:0]   //TL1 */
+       VPU_AXI_WR0,          /* reg4[3:2]   //TL1 */
+       VPU_AFBCE,            /* reg4[5:4]   //TL1 */
+
        VPU_MOD_MAX,
 
        /* for clk_gate */