writel(portsc1, &dev->op_regs->portsc1);
}
+ langwell_udc_notify_otg(
+ MID_OTG_NOTIFY_TEST_MODE_STOP);
+
dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
return;
}
langwell_vbus_draw(&dev->gadget, 0);
case TEST_PACKET:
case TEST_FORCE_EN:
+ langwell_udc_notify_otg(
+ MID_OTG_NOTIFY_TEST_MODE_START);
portsc1 = readl(&dev->op_regs->portsc1);
portsc1 |= req->test_mode << 16;
writel(portsc1, &dev->op_regs->portsc1);
flag = 1;
break;
/* Test mode support */
+ case MID_OTG_NOTIFY_TEST_MODE_START:
+ dev_dbg(pnw->dev, "PNW OTG Notfiy Client Testmode Start\n");
+ iotg->hsm.in_test_mode = 1;
+ flag = 0;
+ break;
+ case MID_OTG_NOTIFY_TEST_MODE_STOP:
+ dev_dbg(pnw->dev, "PNW OTG Notfiy Client Testmode Stop\n");
+ iotg->hsm.in_test_mode = 0;
+ flag = 0;
+ break;
case MID_OTG_NOTIFY_TEST_SRP_REQD:
dev_dbg(pnw->dev, "PNW OTG Notfiy Client SRP REQD\n");
iotg->hsm.otg_srp_reqd = 1;
if (iotg->otg.state != OTG_STATE_B_PERIPHERAL)
return;
+ if (iotg->hsm.in_test_mode)
+ return;
+
if (penwell_otg_ulpi_read(iotg, 0x16, &data)) {
dev_err(pnw->dev, "ulpi read time out by polling\n");
iotg->hsm.ulpi_error = 1;
penwell_otg_eye_diagram_optimize();
/* MFLD WA for PHY issue */
+ iotg->hsm.in_test_mode = 0;
+ iotg->hsm.ulpi_error = 0;
+
if (!is_clovertrail(pdev))
penwell_otg_start_ulpi_poll();
iotg->otg.state = OTG_STATE_A_IDLE;
penwell_update_transceiver();
- } else if (hsm->ulpi_error) {
+ } else if (hsm->ulpi_error && !hsm->in_test_mode) {
/* WA: try to recover once detected PHY issue */
hsm->ulpi_error = 0;
int otg_srp_reqd;
int otg_hnp_reqd;
int otg_vbus_off;
+ int in_test_mode;
};
/* must provide ULPI access function to read/write registers implemented in
#define MID_OTG_NOTIFY_TEST_SRP_REQD 0x0101
#define MID_OTG_NOTIFY_TEST_VBUS_OFF 0x0102
#define MID_OTG_NOTIFY_TEST 0x0103
+#define MID_OTG_NOTIFY_TEST_MODE_START 0x0104
+#define MID_OTG_NOTIFY_TEST_MODE_STOP 0x0105
static inline int
intel_mid_otg_register_notifier(struct intel_mid_otg_xceiv *iotg,