arm64: dts: renesas: r9a07g044: Add CSI and CRU nodes

Add CSI and CRU nodes r9a07g044 (RZ/G2L) SoC DTSI.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230322125648.24948-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index 7b68bbebb5bd8d43df28577d2c067672366a8d36..1315be5167b95b6b0f3de19e77527357a79f6a6f 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -618,6 +618,85 @@
                        status = "disabled";
                };
 
+               cru: video@10830000 {
+                       compatible = "renesas,r9a07g044-cru", "renesas,rzg2l-cru";
+                       reg = <0 0x10830000 0 0x400>;
+                       clocks = <&cpg CPG_MOD R9A07G044_CRU_VCLK>,
+                                <&cpg CPG_MOD R9A07G044_CRU_PCLK>,
+                                <&cpg CPG_MOD R9A07G044_CRU_ACLK>;
+                       clock-names = "video", "apb", "axi";
+                       interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "image_conv", "image_conv_err", "axi_mst_err";
+                       resets = <&cpg R9A07G044_CRU_PRESETN>,
+                                <&cpg R9A07G044_CRU_ARESETN>;
+                       reset-names = "presetn", "aresetn";
+                       power-domains = <&cpg>;
+                       status = "disabled";
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               port@0 {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+
+                                       reg = <0>;
+                                       cruparallel: endpoint@0 {
+                                               reg = <0>;
+                                       };
+                               };
+
+                               port@1 {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+
+                                       reg = <1>;
+                                       crucsi2: endpoint@0 {
+                                               reg = <0>;
+                                               remote-endpoint = <&csi2cru>;
+                                       };
+                               };
+                       };
+               };
+
+               csi2: csi2@10830400 {
+                       compatible = "renesas,r9a07g044-csi2", "renesas,rzg2l-csi2";
+                       reg = <0 0x10830400 0 0xfc00>;
+                       interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD R9A07G044_CRU_SYSCLK>,
+                                <&cpg CPG_MOD R9A07G044_CRU_VCLK>,
+                                <&cpg CPG_MOD R9A07G044_CRU_PCLK>;
+                       clock-names = "system", "video", "apb";
+                       resets = <&cpg R9A07G044_CRU_PRESETN>,
+                                <&cpg R9A07G044_CRU_CMN_RSTB>;
+                       reset-names = "presetn", "cmn-rstb";
+                       power-domains = <&cpg>;
+                       status = "disabled";
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               port@0 {
+                                       reg = <0>;
+                               };
+
+                               port@1 {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+                                       reg = <1>;
+
+                                       csi2cru: endpoint@0 {
+                                               reg = <0>;
+                                               remote-endpoint = <&crucsi2>;
+                                       };
+                               };
+                       };
+               };
+
                cpg: clock-controller@11010000 {
                        compatible = "renesas,r9a07g044-cpg";
                        reg = <0 0x11010000 0 0x10000>;