drm/i915/perf: Do not parse context image for HSW

An earlier commit introduced a mechanism to parse the context image to
find the OA context control offset. This resulted in an NPD on haswell
when gem_context was passed into i915_perf_open_ioctl params. Haswell
does not support logical ring contexts, so ensure that the context image
is parsed only for platforms with logical ring contexts and also
validate lrc_reg_state.

v2: Fix build failure
v3: Fix checkpatch error

Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/7432
Fixes: a5c3a3cbf029 ("drm/i915/perf: Determine gen12 oa ctx offset at runtime")
Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221123235342.713068-1-umesh.nerlige.ramappa@intel.com

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index bee6f3b..963175f 100644 (file)
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1382,6 +1382,9 @@ static u32 oa_context_image_offset(struct intel_context *ce, u32 reg)
        u32 offset, len = (ce->engine->context_size - PAGE_SIZE) / 4;
        u32 *state = ce->lrc_reg_state;
 
+       if (drm_WARN_ON(&ce->engine->i915->drm, !state))
+               return U32_MAX;
+
        for (offset = 0; offset < len; ) {
                if (IS_MI_LRI_CMD(state[offset])) {
                        /*
@@ -1446,7 +1449,8 @@ static int oa_get_render_ctx_id(struct i915_perf_stream *stream)
        if (IS_ERR(ce))
                return PTR_ERR(ce);
 
-       if (engine_supports_mi_query(stream->engine)) {
+       if (engine_supports_mi_query(stream->engine) &&
+           HAS_LOGICAL_RING_CONTEXTS(stream->perf->i915)) {
                /*
                 * We are enabling perf query here. If we don't find the context
                 * offset here, just return an error.