+1998-11-18 Doug Evans <devans@casey.cygnus.com>
+
+ * cgen-asm.in (insert_1): Replace calls to bfd_getb8/putb8.
+ (insert_normal, !CGEN_INT_INSN_P case): Only fetch enough bytes
+ to hold value.
+ (insert_insn_normal): Fix typo.
+ * cgen-dis.c (cgen_dis_lookup_insn): Update type of `value' arg.
+ * cgen-dis.in (extract_normal): Ditto. New arg `pc'.
+ Rewrite ! CGEN_INT_INSN_P case.
+ (extract_insn_normal): Ditto.
+ (extract_1): New arg `pc'. All callers updated.
+ Replace calls to bfd_getb8.
+ (fill_cache): New fn.
+ * cgen-opc.c (cgen_{get,put}_insn_value): Move here ...
+ * cgen-opc.in: ... from here.
+ (@arch@_cgen_lookup_insn): Rewrite ! CGEN_INT_INSN_P case.
+ * m32r-asm.c,m32r-dis.c,m32r-opc.c: Rebuild.
+start-sanitize-fr30
+ * fr30-asm.c,fr30-dis.c,fr30-opc.c: Rebuild.
+end-sanitize-fr30
+
start-sanitize-fr30
Wed Nov 18 11:30:04 1998 Dave Brolley <brolley@cygnus.com>
static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
static unsigned int asm_hash_insn PARAMS ((const char *));
static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
-static unsigned int dis_hash_insn PARAMS ((const char *, unsigned long));
-
-/* Cover function to read and properly byteswap an insn value. */
-
-CGEN_INSN_INT
-cgen_get_insn_value (od, buf, length)
- CGEN_OPCODE_DESC od;
- unsigned char *buf;
- int length;
-{
- CGEN_INSN_INT value;
-
- switch (length)
- {
- case 8:
- value = *buf;
- break;
- case 16:
- if (CGEN_OPCODE_INSN_ENDIAN (od) == CGEN_ENDIAN_BIG)
- value = bfd_getb16 (buf);
- else
- value = bfd_getl16 (buf);
- break;
- case 32:
- if (CGEN_OPCODE_INSN_ENDIAN (od) == CGEN_ENDIAN_BIG)
- value = bfd_getb32 (buf);
- else
- value = bfd_getl32 (buf);
- break;
- default:
- abort ();
- }
-
- return value;
-}
-
-/* Cover function to store an insn value properly byteswapped. */
-
-void
-cgen_put_insn_value (od, buf, length, value)
- CGEN_OPCODE_DESC od;
- unsigned char *buf;
- int length;
- CGEN_INSN_INT value;
-{
- switch (length)
- {
- case 8:
- buf[0] = value;
- break;
- case 16:
- if (CGEN_OPCODE_INSN_ENDIAN (od) == CGEN_ENDIAN_BIG)
- bfd_putb16 (value, buf);
- else
- bfd_putl16 (value, buf);
- break;
- case 32:
- if (CGEN_OPCODE_INSN_ENDIAN (od) == CGEN_ENDIAN_BIG)
- bfd_putb32 (value, buf);
- else
- bfd_putl32 (value, buf);
- break;
- default:
- abort ();
- }
-}
+static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
/* Look up instruction INSN_VALUE and extract its fields.
INSN, if non-null, is the insn table entry.
If INSN != NULL, LENGTH must be valid.
ALIAS_P is non-zero if alias insns are to be included in the search.
- The result a pointer to the insn table entry, or NULL if the instruction
+ The result is a pointer to the insn table entry, or NULL if the instruction
wasn't recognized. */
const CGEN_INSN *
CGEN_FIELDS *fields;
int alias_p;
{
- unsigned char buf[16];
+ unsigned char buf[CGEN_MAX_INSN_SIZE];
unsigned char *bufp;
- unsigned int base_insn;
+ CGEN_INSN_INT base_insn;
#if CGEN_INT_INSN_P
CGEN_EXTRACT_INFO *info = NULL;
#else
CGEN_EXTRACT_INFO *info = &ex_info;
#endif
-#if ! CGEN_INT_INSN_P
+#if CGEN_INT_INSN_P
+ cgen_put_insn_value (od, buf, length, insn_value);
+ bufp = buf;
+ base_insn = insn_value; /*???*/
+#else
ex_info.dis_info = NULL;
- ex_info.bytes = insn_value;
+ ex_info.insn_bytes = insn_value;
ex_info.valid = -1;
+ base_insn = cgen_get_insn_value (od, buf, length);
+ bufp = insn_value;
#endif
if (!insn)
{
const CGEN_INSN_LIST *insn_list;
-#if CGEN_INT_INSN_P
- cgen_put_insn_value (od, buf, length, insn_value);
- bufp = buf;
- base_insn = insn_value; /*???*/
-#else
- base_insn = cgen_get_insn_value (od, buf, length);
- bufp = insn_value;
-#endif
-
/* The instructions are stored in hash lists.
Pick the first one and keep trying until we find the right one. */
/* Basic bit mask must be correct. */
/* ??? May wish to allow target to defer this check until the
extract handler. */
- if ((insn_value & CGEN_INSN_MASK (insn)) == CGEN_INSN_VALUE (insn))
+ if ((base_insn & CGEN_INSN_MASK (insn)) == CGEN_INSN_VALUE (insn))
{
/* ??? 0 is passed for `pc' */
int elength = (*CGEN_EXTRACT_FN (insn)) (od, insn, info,
- insn_value, fields,
+ base_insn, fields,
(bfd_vma) 0);
if (elength > 0)
{
abort ();
/* ??? 0 is passed for `pc' */
- length = (*CGEN_EXTRACT_FN (insn)) (od, insn, info, insn_value, fields,
+ length = (*CGEN_EXTRACT_FN (insn)) (od, insn, info, base_insn, fields,
(bfd_vma) 0);
/* Sanity check: must succeed.
Could relax this later if it ever proves useful. */
case FR30_OPERAND_U10 :
errmsg = cgen_parse_unsigned_integer (od, strp, FR30_OPERAND_U10, &fields->f_u10);
break;
+ case FR30_OPERAND_I32 :
+ errmsg = cgen_parse_unsigned_integer (od, strp, FR30_OPERAND_I32, &fields->f_i32);
+ break;
case FR30_OPERAND_DIR8 :
errmsg = cgen_parse_unsigned_integer (od, strp, FR30_OPERAND_DIR8, &fields->f_dir8);
break;
errmsg = insert_normal (od, value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 8, 8, CGEN_FIELDS_BITSIZE (fields), buffer);
}
break;
+ case FR30_OPERAND_I32 :
+ errmsg = insert_normal (od, fields->f_i32, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), 16, 32, CGEN_FIELDS_BITSIZE (fields), buffer);
+ break;
case FR30_OPERAND_DIR8 :
errmsg = insert_normal (od, fields->f_dir8, 0|(1<<CGEN_OPERAND_UNSIGNED), 8, 8, CGEN_FIELDS_BITSIZE (fields), buffer);
break;
/* ??? This may need reworking as these cases don't necessarily
want the first byte and the last two bytes handled like this. */
if (big_p)
- x = (bfd_getb8 (bufp) << 16) | bfd_getb16 (bufp + 1);
+ x = (bufp[0] << 16) | bfd_getb16 (bufp + 1);
else
- x = bfd_getl16 (bufp) | (bfd_getb8 (bufp + 2) << 16);
+ x = bfd_getl16 (bufp) | (bufp[2] << 16);
break;
case 32:
if (big_p)
want the first byte and the last two bytes handled like this. */
if (big_p)
{
- bfd_putb8 (x >> 16, bufp);
+ bufp[0] = x >> 16;
bfd_putb16 (x, bufp + 1);
}
else
{
bfd_putl16 (x, bufp);
- bfd_putb8 (x >> 16, bufp + 2);
+ bufp[2] = x >> 16;
}
break;
case 32:
The result is an error message or NULL if success. */
-/* ??? May need to know word length in order to properly place values as
- an insn may be made of multiple words and the current bit number handling
- may be insufficient. Word length is an architectural attribute and thus
- methinks the way to go [if needed] is to fetch this value from OD or
- define a macro in <arch>-opc.h rather than adding an extra argument -
- after all that's how endianness is handled. */
/* ??? This duplicates functionality with bfd's howto table and
bfd_install_relocation. */
/* ??? For architectures where insns can be representable as ints,
#if CGEN_INT_INSN_P
- if (total_length > 32)
+ if (total_length > 32) /* 32 bits in a portable host int */
abort ();
{
int shift;
/* FIXME: unfinished and untested */
-/* ??? To be defined in <arch>-opc.h as necessary. */
-#ifndef CGEN_WORD_ENDIAN
-#define CGEN_WORD_ENDIAN(od) CGEN_OPCODE_ENDIAN (od)
-#endif
-#ifndef CGEN_INSN_WORD_ENDIAN
-#define CGEN_INSN_WORD_ENDIAN(od) CGEN_WORD_ENDIAN (od)
-#endif
-
/* The hard case is probably too slow for the normal cases.
It's certainly more difficult to understand than the normal case.
- Thus this is split into two. Keep it that way. The hard case is defined
+ Thus this is split into two. The hard case is defined
to be when a field straddles a (loosely defined) word boundary
(??? which may require target specific help to determine). */
/* Adjust start,total_length,bufp to point to the pseudo-word that holds
the value. For example in a 48 bit insn where the value to insert
- (say an immediate value) is the last 16 bits then word_length here
+ (say an immediate value) is the last 16 bits then fetch_length here
would be 16. To handle a 24 bit insn with an 18 bit immediate,
- insert_1 handles 24 bits (using a combination of bfd_get8,16). */
+ insert_1 handles 24 bits. */
if (total_length > 32)
{
bufp += offset / 8;
start -= offset;
- total_length -= offset;
+ total_length = fetch_length;
}
}
else
bufp += offset / 8;
start -= offset;
- total_length -= offset;
+ total_length = fetch_length;
}
else
{
#else
- cgen_insn_put_value (od, buffer, min (CGEN_BASE_INSN_BITSIZE,
+ cgen_put_insn_value (od, buffer, min (CGEN_BASE_INSN_BITSIZE,
CGEN_FIELDS_BITSIZE (fields)),
value);
#define UNKNOWN_INSN_MSG _("*unknown*")
static int extract_normal
- PARAMS ((CGEN_OPCODE_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_BYTES,
- unsigned int, int, int, int, long *));
+ PARAMS ((CGEN_OPCODE_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
+ unsigned int, int, int, int, bfd_vma, long *));
static void print_normal
PARAMS ((CGEN_OPCODE_DESC, PTR, long, unsigned int, bfd_vma, int));
static void print_address
PARAMS ((CGEN_OPCODE_DESC, PTR, CGEN_KEYWORD *, long, unsigned int));
static int extract_insn_normal
PARAMS ((CGEN_OPCODE_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *,
- unsigned long, CGEN_FIELDS *, bfd_vma));
+ CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma));
static void print_insn_normal
PARAMS ((CGEN_OPCODE_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *,
bfd_vma, int));
CGEN_OPCODE_DESC od;
int opindex;
CGEN_EXTRACT_INFO *ex_info;
- CGEN_INSN_BYTES insn_value;
+ CGEN_INSN_INT insn_value;
CGEN_FIELDS * fields;
bfd_vma pc;
{
switch (opindex)
{
case FR30_OPERAND_RI :
- length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, CGEN_FIELDS_BITSIZE (fields), & fields->f_Ri);
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, CGEN_FIELDS_BITSIZE (fields), pc, & fields->f_Ri);
break;
case FR30_OPERAND_RJ :
- length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 8, 4, CGEN_FIELDS_BITSIZE (fields), & fields->f_Rj);
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 8, 4, CGEN_FIELDS_BITSIZE (fields), pc, & fields->f_Rj);
break;
case FR30_OPERAND_RS1 :
- length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 8, 4, CGEN_FIELDS_BITSIZE (fields), & fields->f_Rs1);
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 8, 4, CGEN_FIELDS_BITSIZE (fields), pc, & fields->f_Rs1);
break;
case FR30_OPERAND_RS2 :
- length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, CGEN_FIELDS_BITSIZE (fields), & fields->f_Rs2);
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, CGEN_FIELDS_BITSIZE (fields), pc, & fields->f_Rs2);
break;
case FR30_OPERAND_R13 :
- length = extract_normal (od, ex_info, insn_value, 0, 0, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_nil);
+ length = extract_normal (od, ex_info, insn_value, 0, 0, 0, CGEN_FIELDS_BITSIZE (fields), pc, & fields->f_nil);
break;
case FR30_OPERAND_R14 :
- length = extract_normal (od, ex_info, insn_value, 0, 0, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_nil);
+ length = extract_normal (od, ex_info, insn_value, 0, 0, 0, CGEN_FIELDS_BITSIZE (fields), pc, & fields->f_nil);
break;
case FR30_OPERAND_R15 :
- length = extract_normal (od, ex_info, insn_value, 0, 0, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_nil);
+ length = extract_normal (od, ex_info, insn_value, 0, 0, 0, CGEN_FIELDS_BITSIZE (fields), pc, & fields->f_nil);
break;
case FR30_OPERAND_PS :
- length = extract_normal (od, ex_info, insn_value, 0, 0, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_nil);
+ length = extract_normal (od, ex_info, insn_value, 0, 0, 0, CGEN_FIELDS_BITSIZE (fields), pc, & fields->f_nil);
break;
case FR30_OPERAND_U4 :
- length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 8, 4, CGEN_FIELDS_BITSIZE (fields), & fields->f_u4);
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 8, 4, CGEN_FIELDS_BITSIZE (fields), pc, & fields->f_u4);
break;
case FR30_OPERAND_M4 :
{
long value;
- length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 8, 4, CGEN_FIELDS_BITSIZE (fields), & value);
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 8, 4, CGEN_FIELDS_BITSIZE (fields), pc, & value);
value = ((value) | ((! (15))));
fields->f_m4 = value;
}
break;
case FR30_OPERAND_U8 :
- length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 8, 8, CGEN_FIELDS_BITSIZE (fields), & fields->f_u8);
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 8, 8, CGEN_FIELDS_BITSIZE (fields), pc, & fields->f_u8);
break;
case FR30_OPERAND_I8 :
- length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 4, 8, CGEN_FIELDS_BITSIZE (fields), & fields->f_i8);
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 4, 8, CGEN_FIELDS_BITSIZE (fields), pc, & fields->f_i8);
break;
case FR30_OPERAND_UDISP6 :
{
long value;
- length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 8, 4, CGEN_FIELDS_BITSIZE (fields), & value);
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 8, 4, CGEN_FIELDS_BITSIZE (fields), pc, & value);
value = ((value) << (2));
fields->f_udisp6 = value;
}
break;
case FR30_OPERAND_DISP8 :
- length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), 4, 8, CGEN_FIELDS_BITSIZE (fields), & fields->f_disp8);
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), 4, 8, CGEN_FIELDS_BITSIZE (fields), pc, & fields->f_disp8);
break;
case FR30_OPERAND_DISP9 :
{
long value;
- length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), 4, 8, CGEN_FIELDS_BITSIZE (fields), & value);
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), 4, 8, CGEN_FIELDS_BITSIZE (fields), pc, & value);
value = ((value) << (1));
fields->f_disp9 = value;
}
case FR30_OPERAND_DISP10 :
{
long value;
- length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), 4, 8, CGEN_FIELDS_BITSIZE (fields), & value);
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), 4, 8, CGEN_FIELDS_BITSIZE (fields), pc, & value);
value = ((value) << (2));
fields->f_disp10 = value;
}
case FR30_OPERAND_S10 :
{
long value;
- length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), 8, 8, CGEN_FIELDS_BITSIZE (fields), & value);
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), 8, 8, CGEN_FIELDS_BITSIZE (fields), pc, & value);
value = ((value) << (2));
fields->f_s10 = value;
}
case FR30_OPERAND_U10 :
{
long value;
- length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 8, 8, CGEN_FIELDS_BITSIZE (fields), & value);
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 8, 8, CGEN_FIELDS_BITSIZE (fields), pc, & value);
value = ((value) << (2));
fields->f_u10 = value;
}
break;
+ case FR30_OPERAND_I32 :
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), 16, 32, CGEN_FIELDS_BITSIZE (fields), pc, & fields->f_i32);
+ break;
case FR30_OPERAND_DIR8 :
- length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 8, 8, CGEN_FIELDS_BITSIZE (fields), & fields->f_dir8);
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 8, 8, CGEN_FIELDS_BITSIZE (fields), pc, & fields->f_dir8);
break;
case FR30_OPERAND_DIR9 :
{
long value;
- length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 8, 8, CGEN_FIELDS_BITSIZE (fields), & value);
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 8, 8, CGEN_FIELDS_BITSIZE (fields), pc, & value);
value = ((value) << (1));
fields->f_dir9 = value;
}
case FR30_OPERAND_DIR10 :
{
long value;
- length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 8, 8, CGEN_FIELDS_BITSIZE (fields), & value);
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 8, 8, CGEN_FIELDS_BITSIZE (fields), pc, & value);
value = ((value) << (2));
fields->f_dir10 = value;
}
case FR30_OPERAND_LABEL9 :
{
long value;
- length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_SIGNED), 8, 8, CGEN_FIELDS_BITSIZE (fields), & value);
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_SIGNED), 8, 8, CGEN_FIELDS_BITSIZE (fields), pc, & value);
value = ((((value) << (1))) + (((pc) & (-2))));
fields->f_rel9 = value;
}
case FR30_OPERAND_LABEL12 :
{
long value;
- length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_SIGNED), 5, 11, CGEN_FIELDS_BITSIZE (fields), & value);
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_SIGNED), 5, 11, CGEN_FIELDS_BITSIZE (fields), pc, & value);
value = ((((value) << (1))) + (((pc) & (-2))));
fields->f_rel12 = value;
}
break;
case FR30_OPERAND_CC :
- length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, CGEN_FIELDS_BITSIZE (fields), & fields->f_cc);
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, CGEN_FIELDS_BITSIZE (fields), pc, & fields->f_cc);
break;
default :
case FR30_OPERAND_U10 :
print_normal (od, info, fields->f_u10, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
break;
+ case FR30_OPERAND_I32 :
+ print_normal (od, info, fields->f_i32, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
+ break;
case FR30_OPERAND_DIR8 :
print_normal (od, info, fields->f_dir8, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
break;
\f
#if ! CGEN_INT_INSN_P
+/* Subroutine of extract_normal.
+ Ensure sufficient bytes are cached in EX_INFO.
+ Returns 1 for success, 0 for failure. */
+
+static INLINE int
+fill_cache (od, ex_info, offset, bytes, pc)
+ CGEN_OPCODE_DESC od;
+ CGEN_EXTRACT_INFO *ex_info;
+ int offset, bytes;
+ bfd_vma pc;
+{
+ /* It's doubtful that the middle part has already been fetched so
+ we don't optimize that case. kiss. */
+ int mask;
+ disassemble_info *info = (disassemble_info *) ex_info->dis_info;
+
+ /* First do a quick check. */
+ mask = (1 << bytes) - 1;
+ if (((ex_info->valid >> offset) & mask) == mask)
+ return 1;
+
+ /* Search for the first byte we need to read. */
+ for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1)
+ if (! (mask & ex_info->valid))
+ break;
+
+ if (bytes)
+ {
+ int status;
+
+ pc += offset;
+ status = (*info->read_memory_func)
+ (pc, ex_info->insn_bytes + offset, bytes, info);
+
+ if (status != 0)
+ {
+ (*info->memory_error_func) (status, pc, info);
+ return 0;
+ }
+
+ ex_info->valid |= ((1 << bytes) - 1) << offset;
+ }
+
+ return 1;
+}
+
/* Subroutine of extract_normal. */
static INLINE long
-extract_1 (od, ex_info, start, length, word_length, bufp)
+extract_1 (od, ex_info, start, length, word_length, bufp, pc)
CGEN_OPCODE_DESC od;
- CGEN_EXTRACT_INFO *info;
+ CGEN_EXTRACT_INFO *ex_info;
int start,length,word_length;
unsigned char *bufp;
+ bfd_vma pc;
{
unsigned long x,mask;
int shift;
int big_p = CGEN_OPCODE_INSN_ENDIAN (od) == CGEN_ENDIAN_BIG;
- /* FIXME: Need to use ex_info to ensure bytes have been fetched. */
-
switch (word_length)
{
case 8:
/* ??? This may need reworking as these cases don't necessarily
want the first byte and the last two bytes handled like this. */
if (big_p)
- x = (bfd_getb8 (bufp) << 16) | bfd_getb16 (bufp + 1);
+ x = (bufp[0] << 16) | bfd_getb16 (bufp + 1);
else
- x = bfd_getl16 (bufp) | (bfd_getb8 (bufp + 2) << 16);
+ x = bfd_getl16 (bufp) | (bufp[2] << 16);
break;
case 32:
if (big_p)
/* Default extraction routine.
+ INSN_VALUE is the first CGEN_BASE_INSN_SIZE bits of the insn in host order,
+ or sometimes less for cases like the m32r where the base insn size is 32
+ but some insns are 16 bits.
ATTRS is a mask of the boolean attributes. We only need `unsigned',
- but for generality we take a bitmask of all of them. */
+ but for generality we take a bitmask of all of them.
+ TOTAL_LENGTH is the length of the insn in bits.
+
+ Returns 1 for success, 0 for failure. */
/* ??? This doesn't handle bfd_vma's. Create another function when
necessary. */
static int
-extract_normal (od, ex_info, insn_value, attrs, start, length, total_length, valuep)
+extract_normal (od, ex_info, insn_value, attrs, start, length, total_length, pc, valuep)
CGEN_OPCODE_DESC od;
CGEN_EXTRACT_INFO *ex_info;
- CGEN_INSN_BYTES insn_value;
+ CGEN_INSN_INT insn_value;
unsigned int attrs;
int start, length, total_length;
+ bfd_vma pc;
long *valuep;
{
unsigned long value;
return 1;
}
-#if CGEN_INT_INSN_P
-
- {
- /* Written this way to avoid undefined behaviour. */
- unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1;
-
- if (CGEN_INSN_LSB0_P)
- value = insn_value >> start;
- else
- value = insn_value >> (total_length - (start + length));
- value &= mask;
- /* sign extend? */
- if (! (attrs & CGEN_ATTR_MASK (CGEN_OPERAND_UNSIGNED))
- && (value & (1L << (length - 1))))
- value |= ~mask;
- }
+ if (CGEN_INT_INSN_P
+ || (CGEN_INSN_LSB0_P
+ ? ((total_length - start) <= CGEN_BASE_INSN_BITSIZE)
+ : ((start + length) <= CGEN_BASE_INSN_BITSIZE)))
+ {
+ /* Written this way to avoid undefined behaviour. */
+ unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1;
-#else
+ if (CGEN_INSN_LSB0_P)
+ value = insn_value >> start;
+ else
+ value = insn_value >> (total_length - (start + length));
+ value &= mask;
+ /* sign extend? */
+ if (! (attrs & CGEN_ATTR_MASK (CGEN_OPERAND_UNSIGNED))
+ && (value & (1L << (length - 1))))
+ value |= ~mask;
+ }
+
+#if ! CGEN_INT_INSN_P
/* The hard case is probably too slow for the normal cases.
It's certainly more difficult to understand than the normal case.
- Thus this is split into two. Keep it that way. The hard case is defined
+ Thus this is split into two. The hard case is defined
to be when a field straddles a (loosely defined) word boundary
(??? which may require target specific help to determine). */
-#if 0 /*wip*/
-
#define HARD_CASE_P 0 /* FIXME:wip */
- if (HARD_CASE_P)
+ else if (HARD_CASE_P)
{
}
-#endif
+
else
{
- unsigned char *bufp = (unsigned char *) insn_value;
+ unsigned char *bufp = ex_info->insn_bytes;
+ int offset = 0;
if (length > 32)
abort ();
/* Adjust start,total_length,bufp to point to the pseudo-word that holds
the value. For example in a 48 bit insn where the value to insert
- (say an immediate value) is the last 16 bits then word_length here
+ (say an immediate value) is the last 16 bits then fetch_length here
would be 16. To handle a 24 bit insn with an 18 bit immediate,
- extract_1 handles 24 bits (using a combination of bfd_get8,16). */
+ extract_1 handles 24 bits. */
if (total_length > 32)
{
}
else
{
- int offset = start & ~7;
+ offset = start & ~7;
bufp += offset / 8;
start -= offset;
- total_length -= offset;
+ total_length = fetch_length;
}
}
else
{
if (CGEN_INSN_WORD_ENDIAN (od) == CGEN_ENDIAN_BIG)
{
- int offset = start & ~7;
+ offset = start & ~7;
bufp += offset / 8;
start -= offset;
- total_length -= offset;
+ total_length = fetch_length;
}
else
{
}
}
- /* FIXME: which bytes are being extracted have been lost. */
- value = extract_1 (od, ex_info, start, length, total_length, bufp);
+ if (fill_cache (od, ex_info, offset / 8, total_length / 8, pc) == 0)
+ return 0;
+
+ value = extract_1 (od, ex_info, start, length, total_length, bufp, pc);
}
#endif /* ! CGEN_INT_INSN_P */
*valuep = value;
- /* FIXME: for now */
return 1;
}
CGEN_OPCODE_DESC od;
const CGEN_INSN *insn;
CGEN_EXTRACT_INFO *ex_info;
- unsigned long insn_value;
+ CGEN_INSN_INT insn_value;
CGEN_FIELDS *fields;
bfd_vma pc;
{
ex_info.dis_info = info;
ex_info.valid = (1 << CGEN_BASE_INSN_SIZE) - 1;
- ex_info.bytes = buf;
+ ex_info.insn_bytes = buf;
switch (buflen)
{
static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
static unsigned int asm_hash_insn PARAMS ((const char *));
static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
-static unsigned int dis_hash_insn PARAMS ((const char *, unsigned long));
-
-/* Cover function to read and properly byteswap an insn value. */
-
-CGEN_INSN_INT
-cgen_get_insn_value (od, buf, length)
- CGEN_OPCODE_DESC od;
- unsigned char *buf;
- int length;
-{
- CGEN_INSN_INT value;
-
- switch (length)
- {
- case 8:
- value = *buf;
- break;
- case 16:
- if (CGEN_OPCODE_INSN_ENDIAN (od) == CGEN_ENDIAN_BIG)
- value = bfd_getb16 (buf);
- else
- value = bfd_getl16 (buf);
- break;
- case 32:
- if (CGEN_OPCODE_INSN_ENDIAN (od) == CGEN_ENDIAN_BIG)
- value = bfd_getb32 (buf);
- else
- value = bfd_getl32 (buf);
- break;
- default:
- abort ();
- }
-
- return value;
-}
-
-/* Cover function to store an insn value properly byteswapped. */
-
-void
-cgen_put_insn_value (od, buf, length, value)
- CGEN_OPCODE_DESC od;
- unsigned char *buf;
- int length;
- CGEN_INSN_INT value;
-{
- switch (length)
- {
- case 8:
- buf[0] = value;
- break;
- case 16:
- if (CGEN_OPCODE_INSN_ENDIAN (od) == CGEN_ENDIAN_BIG)
- bfd_putb16 (value, buf);
- else
- bfd_putl16 (value, buf);
- break;
- case 32:
- if (CGEN_OPCODE_INSN_ENDIAN (od) == CGEN_ENDIAN_BIG)
- bfd_putb32 (value, buf);
- else
- bfd_putl32 (value, buf);
- break;
- default:
- abort ();
- }
-}
+static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
/* Look up instruction INSN_VALUE and extract its fields.
INSN, if non-null, is the insn table entry.
If INSN != NULL, LENGTH must be valid.
ALIAS_P is non-zero if alias insns are to be included in the search.
- The result a pointer to the insn table entry, or NULL if the instruction
+ The result is a pointer to the insn table entry, or NULL if the instruction
wasn't recognized. */
const CGEN_INSN *
CGEN_FIELDS *fields;
int alias_p;
{
- unsigned char buf[16];
+ unsigned char buf[CGEN_MAX_INSN_SIZE];
unsigned char *bufp;
- unsigned int base_insn;
+ CGEN_INSN_INT base_insn;
#if CGEN_INT_INSN_P
CGEN_EXTRACT_INFO *info = NULL;
#else
CGEN_EXTRACT_INFO *info = &ex_info;
#endif
-#if ! CGEN_INT_INSN_P
+#if CGEN_INT_INSN_P
+ cgen_put_insn_value (od, buf, length, insn_value);
+ bufp = buf;
+ base_insn = insn_value; /*???*/
+#else
ex_info.dis_info = NULL;
- ex_info.bytes = insn_value;
+ ex_info.insn_bytes = insn_value;
ex_info.valid = -1;
+ base_insn = cgen_get_insn_value (od, buf, length);
+ bufp = insn_value;
#endif
if (!insn)
{
const CGEN_INSN_LIST *insn_list;
-#if CGEN_INT_INSN_P
- cgen_put_insn_value (od, buf, length, insn_value);
- bufp = buf;
- base_insn = insn_value; /*???*/
-#else
- base_insn = cgen_get_insn_value (od, buf, length);
- bufp = insn_value;
-#endif
-
/* The instructions are stored in hash lists.
Pick the first one and keep trying until we find the right one. */
/* Basic bit mask must be correct. */
/* ??? May wish to allow target to defer this check until the
extract handler. */
- if ((insn_value & CGEN_INSN_MASK (insn)) == CGEN_INSN_VALUE (insn))
+ if ((base_insn & CGEN_INSN_MASK (insn)) == CGEN_INSN_VALUE (insn))
{
/* ??? 0 is passed for `pc' */
int elength = (*CGEN_EXTRACT_FN (insn)) (od, insn, info,
- insn_value, fields,
+ base_insn, fields,
(bfd_vma) 0);
if (elength > 0)
{
abort ();
/* ??? 0 is passed for `pc' */
- length = (*CGEN_EXTRACT_FN (insn)) (od, insn, info, insn_value, fields,
+ length = (*CGEN_EXTRACT_FN (insn)) (od, insn, info, base_insn, fields,
(bfd_vma) 0);
/* Sanity check: must succeed.
Could relax this later if it ever proves useful. */
/* u10: 10 bit unsigned immediate */
{ "u10", & HW_ENT (HW_H_UINT), 8, 8,
{ 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+/* i32: 32 bit immediate */
+ { "i32", & HW_ENT (HW_H_UINT), 16, 32,
+ { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
/* dir8: 8 bit direct address */
{ "dir8", & HW_ENT (HW_H_UINT), 8, 8,
{ 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
#define INPUT CGEN_OPERAND_INSTANCE_INPUT
#define OUTPUT CGEN_OPERAND_INSTANCE_OUTPUT
+#define COND_REF CGEN_OPERAND_INSTANCE_COND_REF
static const CGEN_OPERAND_INSTANCE fmt_add_ops[] = {
- { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
- { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0 },
- { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0 },
- { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0 },
- { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
- { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0 },
- { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0 },
+ { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
+ { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
+ { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
+ { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
+ { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
+ { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
+ { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
{ 0 }
};
static const CGEN_OPERAND_INSTANCE fmt_addi_ops[] = {
- { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
- { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0 },
- { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0 },
- { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0 },
- { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
- { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0 },
- { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0 },
+ { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
+ { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0, 0 },
+ { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
+ { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
+ { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
+ { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
+ { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
{ 0 }
};
static const CGEN_OPERAND_INSTANCE fmt_add2_ops[] = {
- { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
- { INPUT, "m4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (M4), 0 },
- { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0 },
- { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0 },
- { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
- { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0 },
- { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0 },
+ { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
+ { INPUT, "m4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (M4), 0, 0 },
+ { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
+ { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
+ { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
+ { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
+ { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
{ 0 }
};
static const CGEN_OPERAND_INSTANCE fmt_addc_ops[] = {
- { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
- { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0 },
- { INPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0 },
- { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0 },
- { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0 },
- { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
- { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0 },
- { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0 },
+ { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
+ { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
+ { INPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
+ { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
+ { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
+ { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
+ { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
+ { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
{ 0 }
};
static const CGEN_OPERAND_INSTANCE fmt_addn_ops[] = {
- { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
- { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0 },
- { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
+ { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
+ { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
+ { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
{ 0 }
};
static const CGEN_OPERAND_INSTANCE fmt_addni_ops[] = {
- { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
- { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0 },
- { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
+ { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
+ { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0, 0 },
+ { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
{ 0 }
};
static const CGEN_OPERAND_INSTANCE fmt_addn2_ops[] = {
- { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
- { INPUT, "m4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (M4), 0 },
- { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
+ { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
+ { INPUT, "m4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (M4), 0, 0 },
+ { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
{ 0 }
};
static const CGEN_OPERAND_INSTANCE fmt_cmp_ops[] = {
- { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
- { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0 },
- { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0 },
- { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0 },
- { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0 },
- { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0 },
+ { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
+ { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
+ { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
+ { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
+ { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
+ { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
{ 0 }
};
static const CGEN_OPERAND_INSTANCE fmt_cmpi_ops[] = {
- { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
- { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0 },
- { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0 },
- { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0 },
- { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0 },
- { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0 },
+ { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
+ { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0, 0 },
+ { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
+ { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
+ { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
+ { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
{ 0 }
};
static const CGEN_OPERAND_INSTANCE fmt_cmp2_ops[] = {
- { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
- { INPUT, "m4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (M4), 0 },
- { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0 },
- { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0 },
- { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0 },
- { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0 },
+ { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
+ { INPUT, "m4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (M4), 0, 0 },
+ { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
+ { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
+ { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
+ { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
{ 0 }
};
static const CGEN_OPERAND_INSTANCE fmt_and_ops[] = {
- { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
- { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0 },
- { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0 },
- { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0 },
- { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0 },
+ { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
+ { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
+ { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
+ { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
+ { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
{ 0 }
};
static const CGEN_OPERAND_INSTANCE fmt_andm_ops[] = {
- { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0 },
- { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
- { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0 },
- { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0 },
- { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0 },
- { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
+ { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
+ { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+ { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
+ { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
+ { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
+ { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
{ 0 }
};
static const CGEN_OPERAND_INSTANCE fmt_andh_ops[] = {
- { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0 },
- { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
- { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_HI, & OP_ENT (RJ), 0 },
- { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0 },
- { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0 },
- { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
+ { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
+ { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
+ { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_HI, & OP_ENT (RJ), 0, 0 },
+ { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
+ { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
+ { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
{ 0 }
};
static const CGEN_OPERAND_INSTANCE fmt_andb_ops[] = {
- { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0 },
- { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
- { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_QI, & OP_ENT (RJ), 0 },
- { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0 },
- { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0 },
- { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
+ { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RI), 0, 0 },
+ { INPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
+ { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_QI, & OP_ENT (RJ), 0, 0 },
+ { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
+ { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
+ { OUTPUT, "h_memory_Ri", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
+ { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ldi32_ops[] = {
+ { INPUT, "i32", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (I32), 0, 0 },
+ { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
{ 0 }
};
#undef INPUT
#undef OUTPUT
+#undef COND_REF
#define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
(PTR) 0,
{ 0, 0, { 0 } }
},
+/* ldi:32 $i32,$Ri */
+ {
+ { 1, 1, 1, 1 },
+ FR30_INSN_LDI32, "ldi32", "ldi:32",
+ { { MNEM, ' ', OP (I32), ',', OP (RI), 0 } },
+ { 16, 48, 0xfff0 }, 0x9f80,
+ (PTR) & fmt_ldi32_ops[0],
+ { 0, 0, { 0 } }
+ },
/* ld @$Rj,$Ri */
{
{ 1, 1, 1, 1 },
static unsigned int
dis_hash_insn (buf, value)
const char * buf;
- unsigned long value;
+ CGEN_INSN_INT value;
{
return CGEN_DIS_HASH (buf, value);
}
case FR30_OPERAND_U10 :
value = fields->f_u10;
break;
+ case FR30_OPERAND_I32 :
+ value = fields->f_i32;
+ break;
case FR30_OPERAND_DIR8 :
value = fields->f_dir8;
break;
case FR30_OPERAND_U10 :
value = fields->f_u10;
break;
+ case FR30_OPERAND_I32 :
+ value = fields->f_i32;
+ break;
case FR30_OPERAND_DIR8 :
value = fields->f_dir8;
break;
case FR30_OPERAND_U10 :
fields->f_u10 = value;
break;
+ case FR30_OPERAND_I32 :
+ fields->f_i32 = value;
+ break;
case FR30_OPERAND_DIR8 :
fields->f_dir8 = value;
break;
case FR30_OPERAND_U10 :
fields->f_u10 = value;
break;
+ case FR30_OPERAND_I32 :
+ fields->f_i32 = value;
+ break;
case FR30_OPERAND_DIR8 :
fields->f_dir8 = value;
break;
#define CGEN_DEFAULT_INSN_BITSIZE 16
#define CGEN_BASE_INSN_BITSIZE 16
#define CGEN_MIN_INSN_BITSIZE 16
-#define CGEN_MAX_INSN_BITSIZE 16
+#define CGEN_MAX_INSN_BITSIZE 48
#define CGEN_DEFAULT_INSN_SIZE (CGEN_DEFAULT_INSN_BITSIZE / 8)
#define CGEN_BASE_INSN_SIZE (CGEN_BASE_INSN_BITSIZE / 8)
#define CGEN_MIN_INSN_SIZE (CGEN_MIN_INSN_BITSIZE / 8)
#define CGEN_MAX_INSN_SIZE (CGEN_MAX_INSN_BITSIZE / 8)
-#define CGEN_INT_INSN_P 1
+#define CGEN_INT_INSN_P 0
/* FIXME: Need to compute CGEN_MAX_SYNTAX_BYTES. */
, FR30_OPERAND_RS2, FR30_OPERAND_R13, FR30_OPERAND_R14, FR30_OPERAND_R15
, FR30_OPERAND_PS, FR30_OPERAND_U4, FR30_OPERAND_M4, FR30_OPERAND_U8
, FR30_OPERAND_I8, FR30_OPERAND_UDISP6, FR30_OPERAND_DISP8, FR30_OPERAND_DISP9
- , FR30_OPERAND_DISP10, FR30_OPERAND_S10, FR30_OPERAND_U10, FR30_OPERAND_DIR8
- , FR30_OPERAND_DIR9, FR30_OPERAND_DIR10, FR30_OPERAND_LABEL9, FR30_OPERAND_LABEL12
- , FR30_OPERAND_CC, FR30_OPERAND_NBIT, FR30_OPERAND_VBIT, FR30_OPERAND_ZBIT
- , FR30_OPERAND_CBIT, FR30_OPERAND_MAX
+ , FR30_OPERAND_DISP10, FR30_OPERAND_S10, FR30_OPERAND_U10, FR30_OPERAND_I32
+ , FR30_OPERAND_DIR8, FR30_OPERAND_DIR9, FR30_OPERAND_DIR10, FR30_OPERAND_LABEL9
+ , FR30_OPERAND_LABEL12, FR30_OPERAND_CC, FR30_OPERAND_NBIT, FR30_OPERAND_VBIT
+ , FR30_OPERAND_ZBIT, FR30_OPERAND_CBIT, FR30_OPERAND_MAX
} CGEN_OPERAND_TYPE;
/* Non-boolean attributes. */
, FR30_INSN_DIV1, FR30_INSN_DIV2, FR30_INSN_DIV3, FR30_INSN_DIV4S
, FR30_INSN_LSL, FR30_INSN_LSLI, FR30_INSN_LSL2, FR30_INSN_LSR
, FR30_INSN_LSRI, FR30_INSN_LSR2, FR30_INSN_ASR, FR30_INSN_ASRI
- , FR30_INSN_ASR2, FR30_INSN_LDI_8, FR30_INSN_LD, FR30_INSN_LDUH
- , FR30_INSN_LDUB, FR30_INSN_LDR13, FR30_INSN_LDR13UH, FR30_INSN_LDR13UB
- , FR30_INSN_LDR14, FR30_INSN_LDR14UH, FR30_INSN_LDR14UB, FR30_INSN_LDR15
- , FR30_INSN_LDR15GR, FR30_INSN_LDR15DR, FR30_INSN_LDR15PS, FR30_INSN_ST
- , FR30_INSN_STH, FR30_INSN_STB, FR30_INSN_STR13, FR30_INSN_STR13H
- , FR30_INSN_STR13B, FR30_INSN_STR14, FR30_INSN_STR14H, FR30_INSN_STR14B
- , FR30_INSN_STR15, FR30_INSN_STR15GR, FR30_INSN_STR15DR, FR30_INSN_STR15PS
- , FR30_INSN_MOV, FR30_INSN_MOVDR, FR30_INSN_MOVPS, FR30_INSN_MOV2DR
- , FR30_INSN_MOV2PS, FR30_INSN_JMP, FR30_INSN_JMPD, FR30_INSN_CALL
- , FR30_INSN_CALLD, FR30_INSN_CALLR, FR30_INSN_CALLRD, FR30_INSN_RET
- , FR30_INSN_RETD, FR30_INSN_INT, FR30_INSN_INTE, FR30_INSN_RETI
- , FR30_INSN_BRA, FR30_INSN_BNO, FR30_INSN_BEQ, FR30_INSN_BNE
- , FR30_INSN_BC, FR30_INSN_BNC, FR30_INSN_BN, FR30_INSN_BP
- , FR30_INSN_BV, FR30_INSN_BNV, FR30_INSN_BLT, FR30_INSN_BGE
- , FR30_INSN_BLE, FR30_INSN_BGT, FR30_INSN_BLS, FR30_INSN_BHI
- , FR30_INSN_BRAD, FR30_INSN_BNOD, FR30_INSN_BEQD, FR30_INSN_BNED
- , FR30_INSN_BCD, FR30_INSN_BNCD, FR30_INSN_BND, FR30_INSN_BPD
- , FR30_INSN_BVD, FR30_INSN_BNVD, FR30_INSN_BLTD, FR30_INSN_BGED
- , FR30_INSN_BLED, FR30_INSN_BGTD, FR30_INSN_BLSD, FR30_INSN_BHID
- , FR30_INSN_DMOV2R13, FR30_INSN_DMOV2R13H, FR30_INSN_DMOV2R13B, FR30_INSN_DMOVR13
- , FR30_INSN_DMOVR13H, FR30_INSN_DMOVR13B, FR30_INSN_DMOV2R13PI, FR30_INSN_DMOV2R13PIH
- , FR30_INSN_DMOV2R13PIB, FR30_INSN_DMOVR13PI, FR30_INSN_DMOVR13PIH, FR30_INSN_DMOVR13PIB
- , FR30_INSN_DMOV2R15PD, FR30_INSN_DMOVR15PI, FR30_INSN_LDRES, FR30_INSN_STRES
- , FR30_INSN_NOP, FR30_INSN_ANDCCR, FR30_INSN_ORCCR, FR30_INSN_STILM
- , FR30_INSN_ADDSP, FR30_INSN_EXTSB, FR30_INSN_EXTUB, FR30_INSN_EXTSH
- , FR30_INSN_EXTUH, FR30_INSN_ENTER, FR30_INSN_LEAVE, FR30_INSN_XCHB
- , FR30_INSN_MAX
+ , FR30_INSN_ASR2, FR30_INSN_LDI_8, FR30_INSN_LDI32, FR30_INSN_LD
+ , FR30_INSN_LDUH, FR30_INSN_LDUB, FR30_INSN_LDR13, FR30_INSN_LDR13UH
+ , FR30_INSN_LDR13UB, FR30_INSN_LDR14, FR30_INSN_LDR14UH, FR30_INSN_LDR14UB
+ , FR30_INSN_LDR15, FR30_INSN_LDR15GR, FR30_INSN_LDR15DR, FR30_INSN_LDR15PS
+ , FR30_INSN_ST, FR30_INSN_STH, FR30_INSN_STB, FR30_INSN_STR13
+ , FR30_INSN_STR13H, FR30_INSN_STR13B, FR30_INSN_STR14, FR30_INSN_STR14H
+ , FR30_INSN_STR14B, FR30_INSN_STR15, FR30_INSN_STR15GR, FR30_INSN_STR15DR
+ , FR30_INSN_STR15PS, FR30_INSN_MOV, FR30_INSN_MOVDR, FR30_INSN_MOVPS
+ , FR30_INSN_MOV2DR, FR30_INSN_MOV2PS, FR30_INSN_JMP, FR30_INSN_JMPD
+ , FR30_INSN_CALL, FR30_INSN_CALLD, FR30_INSN_CALLR, FR30_INSN_CALLRD
+ , FR30_INSN_RET, FR30_INSN_RETD, FR30_INSN_INT, FR30_INSN_INTE
+ , FR30_INSN_RETI, FR30_INSN_BRA, FR30_INSN_BNO, FR30_INSN_BEQ
+ , FR30_INSN_BNE, FR30_INSN_BC, FR30_INSN_BNC, FR30_INSN_BN
+ , FR30_INSN_BP, FR30_INSN_BV, FR30_INSN_BNV, FR30_INSN_BLT
+ , FR30_INSN_BGE, FR30_INSN_BLE, FR30_INSN_BGT, FR30_INSN_BLS
+ , FR30_INSN_BHI, FR30_INSN_BRAD, FR30_INSN_BNOD, FR30_INSN_BEQD
+ , FR30_INSN_BNED, FR30_INSN_BCD, FR30_INSN_BNCD, FR30_INSN_BND
+ , FR30_INSN_BPD, FR30_INSN_BVD, FR30_INSN_BNVD, FR30_INSN_BLTD
+ , FR30_INSN_BGED, FR30_INSN_BLED, FR30_INSN_BGTD, FR30_INSN_BLSD
+ , FR30_INSN_BHID, FR30_INSN_DMOV2R13, FR30_INSN_DMOV2R13H, FR30_INSN_DMOV2R13B
+ , FR30_INSN_DMOVR13, FR30_INSN_DMOVR13H, FR30_INSN_DMOVR13B, FR30_INSN_DMOV2R13PI
+ , FR30_INSN_DMOV2R13PIH, FR30_INSN_DMOV2R13PIB, FR30_INSN_DMOVR13PI, FR30_INSN_DMOVR13PIH
+ , FR30_INSN_DMOVR13PIB, FR30_INSN_DMOV2R15PD, FR30_INSN_DMOVR15PI, FR30_INSN_LDRES
+ , FR30_INSN_STRES, FR30_INSN_NOP, FR30_INSN_ANDCCR, FR30_INSN_ORCCR
+ , FR30_INSN_STILM, FR30_INSN_ADDSP, FR30_INSN_EXTSB, FR30_INSN_EXTUB
+ , FR30_INSN_EXTSH, FR30_INSN_EXTUH, FR30_INSN_ENTER, FR30_INSN_LEAVE
+ , FR30_INSN_XCHB, FR30_INSN_MAX
} CGEN_INSN_TYPE;
/* Index of `invalid' insn place holder. */
long f_m4;
long f_u8;
long f_i8;
+ long f_i32;
long f_udisp6;
long f_disp8;
long f_disp9;
projects / platform / upstream / binutils.git / commitdiff