clk: imx: clk-imx8qxp: Add SCU clocks support for DC0 PLL clocks
authorLiu Ying <victor.liu@nxp.com>
Wed, 2 Dec 2020 05:33:36 +0000 (13:33 +0800)
committerShawn Guo <shawnguo@kernel.org>
Tue, 5 Jan 2021 02:54:37 +0000 (10:54 +0800)
This patch adds SCU clocks support for i.MX8qxp DC0 subsystem PLL clocks.

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
drivers/clk/imx/clk-imx8qxp.c

index 5b3d4ed..b48643e 100644 (file)
@@ -117,6 +117,8 @@ static int imx8qxp_clk_probe(struct platform_device *pdev)
        /* Display controller SS */
        clks[IMX_DC0_DISP0_CLK]         = imx_clk_scu("dc0_disp0_clk", IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC0, clk_cells);
        clks[IMX_DC0_DISP1_CLK]         = imx_clk_scu("dc0_disp1_clk", IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC1, clk_cells);
+       clks[IMX_DC0_PLL0_CLK]          = imx_clk_scu("dc0_pll0_clk", IMX_SC_R_DC_0_PLL_0, IMX_SC_PM_CLK_PLL, clk_cells);
+       clks[IMX_DC0_PLL1_CLK]          = imx_clk_scu("dc0_pll1_clk", IMX_SC_R_DC_0_PLL_1, IMX_SC_PM_CLK_PLL, clk_cells);
 
        /* MIPI-LVDS SS */
        clks[IMX_MIPI0_I2C0_CLK]        = imx_clk_scu("mipi0_i2c0_clk", IMX_SC_R_MIPI_0_I2C_0, IMX_SC_PM_CLK_MISC2, clk_cells);