2012-03-19 H.J. Lu <hongjiu.lu@intel.com>
+ * sysdeps/x86_64/bits/atomic.h
+ (__arch_c_compare_and_exchange_val_64_acq): Use atomic64_t on
+ 64bit integer.
+ (atomic_exchange_acq): Likewise.
+ (__arch_exchange_and_add_body): Likewise.
+ (__arch_add_body): Likewise.
+ (atomic_add_negative): Likewise.
+ (atomic_add_zero): Likewise.
+
+2012-03-19 H.J. Lu <hongjiu.lu@intel.com>
+
* sysdeps/x86_64/bits/mathdef.h: Don't include <bits/wordsize.h>.
(fenv_t): Check __x86_64__ instead of __WORDSIZE.
"lock\n" \
"0:\tcmpxchgq %q2, %1" \
: "=a" (ret), "=m" (*mem) \
- : "q" ((long int) (newval)), "m" (*mem), \
- "0" ((long int)oldval), \
+ : "q" ((atomic64_t) (newval)), "m" (*mem), \
+ "0" ((atomic64_t) (oldval)), \
"i" (offsetof (tcbhead_t, multiple_threads))); \
ret; })
else \
__asm __volatile ("xchgq %q0, %1" \
: "=r" (result), "=m" (*mem) \
- : "0" ((long) (newvalue)), "m" (*mem)); \
+ : "0" ((atomic64_t) (newvalue)), "m" (*mem)); \
result; })
else \
__asm __volatile (lock "xaddq %q0, %1" \
: "=r" (result), "=m" (*mem) \
- : "0" ((long) (value)), "m" (*mem), \
+ : "0" ((atomic64_t) (value)), "m" (*mem), \
"i" (offsetof (tcbhead_t, multiple_threads))); \
result; })
else \
__asm __volatile (lock "addq %q1, %0" \
: "=m" (*mem) \
- : "ir" ((long) (value)), "m" (*mem), \
+ : "ir" ((atomic64_t) (value)), "m" (*mem), \
"i" (offsetof (tcbhead_t, multiple_threads))); \
} while (0)
else \
__asm __volatile (LOCK_PREFIX "addq %q2, %0; sets %1" \
: "=m" (*mem), "=qm" (__result) \
- : "ir" ((long) (value)), "m" (*mem)); \
+ : "ir" ((atomic64_t) (value)), "m" (*mem)); \
__result; })
else \
__asm __volatile (LOCK_PREFIX "addq %q2, %0; setz %1" \
: "=m" (*mem), "=qm" (__result) \
- : "ir" ((long) (value)), "m" (*mem)); \
+ : "ir" ((atomic64_t) (value)), "m" (*mem)); \
__result; })