bool rast_state_changed : 1;
bool dsa_state_changed : 1;
bool stencil_ref_changed : 1;
+ bool rasterizer_discard_changed : 1;
};
static inline struct zink_context *
ctx->primitive_restart = dinfo->primitive_restart;
}
+ if (DYNAMIC_STATE >= ZINK_DYNAMIC_STATE2 && (BATCH_CHANGED || ctx->rasterizer_discard_changed)) {
+ VKCTX(CmdSetRasterizerDiscardEnableEXT)(batch->state->cmdbuf, ctx->gfx_pipeline_state.dyn_state2.rasterizer_discard);
+ ctx->rasterizer_discard_changed = false;
+ }
+
if (zink_program_has_descriptors(&ctx->curr_program->base))
screen->descriptors_update(ctx, false);
rast_state.sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO;
rast_state.depthClampEnable = hw_rast_state->depth_clamp;
- rast_state.rasterizerDiscardEnable = hw_rast_state->rasterizer_discard;
+ rast_state.rasterizerDiscardEnable = state->dyn_state2.rasterizer_discard;
rast_state.polygonMode = hw_rast_state->polygon_mode;
rast_state.cullMode = hw_rast_state->cull_mode;
rast_state.frontFace = state->dyn_state1.front_face;
else if (screen->info.have_EXT_extended_dynamic_state)
dynamicStateEnables[state_count++] = VK_DYNAMIC_STATE_VERTEX_INPUT_BINDING_STRIDE_EXT;
}
- if (screen->info.have_EXT_extended_dynamic_state2)
+ if (screen->info.have_EXT_extended_dynamic_state2) {
dynamicStateEnables[state_count++] = VK_DYNAMIC_STATE_PRIMITIVE_RESTART_ENABLE_EXT;
+ dynamicStateEnables[state_count++] = VK_DYNAMIC_STATE_RASTERIZER_DISCARD_ENABLE_EXT;
+ }
VkPipelineRasterizationLineStateCreateInfoEXT rast_line_state;
if (screen->info.have_EXT_line_rasterization) {
struct zink_gfx_pipeline_state {
uint32_t rast_state : ZINK_RAST_HW_STATE_SIZE; //zink_rasterizer_hw_state
uint32_t vertices_per_patch:5;
- uint32_t rast_samples:7;
+ uint32_t rast_samples:8; //2 extra bits
uint32_t void_alpha_attachments:PIPE_MAX_COLOR_BUFS;
VkSampleMask sample_mask;
struct {
bool primitive_restart;
+ bool rasterizer_discard;
} dyn_state2;
VkShaderModule modules[PIPE_SHADER_TYPES - 1];
assert(rs_state->depth_clip_far == rs_state->depth_clip_near);
state->hw_state.depth_clamp = rs_state->depth_clip_near == 0;
- state->hw_state.rasterizer_discard = rs_state->rasterizer_discard;
state->hw_state.force_persample_interp = rs_state->force_persample_interp;
state->hw_state.pv_last = !rs_state->flatshade_first;
state->hw_state.clip_halfz = rs_state->clip_halfz;
ctx->gfx_pipeline_state.dyn_state1.front_face = ctx->rast_state->front_face;
ctx->gfx_pipeline_state.dirty |= !zink_screen(pctx->screen)->info.have_EXT_extended_dynamic_state;
}
+ if (ctx->gfx_pipeline_state.dyn_state2.rasterizer_discard != ctx->rast_state->base.rasterizer_discard) {
+ ctx->gfx_pipeline_state.dyn_state2.rasterizer_discard = ctx->rast_state->base.rasterizer_discard;
+ ctx->gfx_pipeline_state.dirty |= !zink_screen(pctx->screen)->info.have_EXT_extended_dynamic_state2;
+ if (zink_screen(pctx->screen)->info.have_EXT_extended_dynamic_state2)
+ ctx->rasterizer_discard_changed = true;
+ }
if (ctx->rast_state->base.point_quad_rasterization != point_quad_rasterization)
zink_set_fs_point_coord_key(ctx);
if (ctx->rast_state->base.scissor != scissor)
unsigned cull_mode : 2; //VkCullModeFlags
unsigned line_mode : 2; //VkLineRasterizationModeEXT
unsigned depth_clamp:1;
- unsigned rasterizer_discard:1;
unsigned pv_last:1;
unsigned line_stipple_enable:1;
unsigned force_persample_interp:1;
unsigned clip_halfz:1;
};
-#define ZINK_RAST_HW_STATE_SIZE 12
+#define ZINK_RAST_HW_STATE_SIZE 11
struct zink_rasterizer_state {