x86/boot: Use MSR read/write helpers instead of inline assembly

Update all C code to use the new boot_rdmsr()/boot_wrmsr() helpers
instead of relying on inline assembly.

Suggested-by: Borislav Petkov <bp@alien8.de>
Signed-off-by: Michael Roth <michael.roth@amd.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Link: https://lore.kernel.org/r/20220307213356.2797205-7-brijesh.singh@amd.com

diff --git a/arch/x86/boot/compressed/sev.c b/arch/x86/boot/compressed/sev.c
index 28bcf04..4e82101 100644 (file)
--- a/arch/x86/boot/compressed/sev.c
+++ b/arch/x86/boot/compressed/sev.c
@@ -22,6 +22,7 @@
 #include <asm/svm.h>
 
 #include "error.h"
+#include "../msr.h"
 
 struct ghcb boot_ghcb_page __aligned(PAGE_SIZE);
 struct ghcb *boot_ghcb;
@@ -56,23 +57,19 @@ static unsigned long insn_get_seg_base(struct pt_regs *regs, int seg_reg_idx)
 
 static inline u64 sev_es_rd_ghcb_msr(void)
 {
-       unsigned long low, high;
+       struct msr m;
 
-       asm volatile("rdmsr" : "=a" (low), "=d" (high) :
-                       "c" (MSR_AMD64_SEV_ES_GHCB));
+       boot_rdmsr(MSR_AMD64_SEV_ES_GHCB, &m);
 
-       return ((high << 32) | low);
+       return m.q;
 }
 
 static inline void sev_es_wr_ghcb_msr(u64 val)
 {
-       u32 low, high;
+       struct msr m;
 
-       low  = val & 0xffffffffUL;
-       high = val >> 32;
-
-       asm volatile("wrmsr" : : "c" (MSR_AMD64_SEV_ES_GHCB),
-                       "a"(low), "d" (high) : "memory");
+       m.q = val;
+       boot_wrmsr(MSR_AMD64_SEV_ES_GHCB, &m);
 }
 
 static enum es_result vc_decode_insn(struct es_em_ctxt *ctxt)

diff --git a/arch/x86/boot/cpucheck.c b/arch/x86/boot/cpucheck.c
index e1478d3..fed8d13 100644 (file)
--- a/arch/x86/boot/cpucheck.c
+++ b/arch/x86/boot/cpucheck.c
@@ -27,6 +27,7 @@
 #include <asm/required-features.h>
 #include <asm/msr-index.h>
 #include "string.h"
+#include "msr.h"
 
 static u32 err_flags[NCAPINTS];
 
@@ -130,12 +131,11 @@ int check_cpu(int *cpu_level_ptr, int *req_level_ptr, u32 **err_flags_ptr)
                /* If this is an AMD and we're only missing SSE+SSE2, try to
                   turn them on */
 
-               u32 ecx = MSR_K7_HWCR;
-               u32 eax, edx;
+               struct msr m;
 
-               asm("rdmsr" : "=a" (eax), "=d" (edx) : "c" (ecx));
-               eax &= ~(1 << 15);
-               asm("wrmsr" : : "a" (eax), "d" (edx), "c" (ecx));
+               boot_rdmsr(MSR_K7_HWCR, &m);
+               m.l &= ~(1 << 15);
+               boot_wrmsr(MSR_K7_HWCR, &m);
 
                get_cpuflags(); /* Make sure it really did something */
                err = check_cpuflags();
@@ -145,28 +145,28 @@ int check_cpu(int *cpu_level_ptr, int *req_level_ptr, u32 **err_flags_ptr)
                /* If this is a VIA C3, we might have to enable CX8
                   explicitly */
 
-               u32 ecx = MSR_VIA_FCR;
-               u32 eax, edx;
+               struct msr m;
 
-               asm("rdmsr" : "=a" (eax), "=d" (edx) : "c" (ecx));
-               eax |= (1<<1)|(1<<7);
-               asm("wrmsr" : : "a" (eax), "d" (edx), "c" (ecx));
+               boot_rdmsr(MSR_VIA_FCR, &m);
+               m.l |= (1 << 1) | (1 << 7);
+               boot_wrmsr(MSR_VIA_FCR, &m);
 
                set_bit(X86_FEATURE_CX8, cpu.flags);
                err = check_cpuflags();
        } else if (err == 0x01 && is_transmeta()) {
                /* Transmeta might have masked feature bits in word 0 */
 
-               u32 ecx = 0x80860004;
-               u32 eax, edx;
+               struct msr m, m_tmp;
                u32 level = 1;
 
-               asm("rdmsr" : "=a" (eax), "=d" (edx) : "c" (ecx));
-               asm("wrmsr" : : "a" (~0), "d" (edx), "c" (ecx));
+               boot_rdmsr(0x80860004, &m);
+               m_tmp = m;
+               m_tmp.l = ~0;
+               boot_wrmsr(0x80860004, &m_tmp);
                asm("cpuid"
                    : "+a" (level), "=d" (cpu.flags[0])
                    : : "ecx", "ebx");
-               asm("wrmsr" : : "a" (eax), "d" (edx), "c" (ecx));
+               boot_wrmsr(0x80860004, &m);
 
                err = check_cpuflags();
        } else if (err == 0x01 &&