bool rast_state_changed = ctx->rast_state_changed;
if (HAS_DYNAMIC_STATE && (BATCH_CHANGED || rast_state_changed))
- screen->vk.CmdSetFrontFaceEXT(batch->state->cmdbuf, ctx->gfx_pipeline_state.front_face);
+ screen->vk.CmdSetFrontFaceEXT(batch->state->cmdbuf, ctx->gfx_pipeline_state.dyn_state1.front_face);
if ((BATCH_CHANGED || rast_state_changed) &&
screen->info.have_EXT_line_rasterization && rast_state->base.line_stipple_enable)
screen->vk.CmdSetLineStippleEXT(batch->state->cmdbuf, rast_state->base.line_stipple_factor, rast_state->base.line_stipple_pattern);
rast_state.rasterizerDiscardEnable = state->rast_state->rasterizer_discard;
rast_state.polygonMode = state->rast_state->polygon_mode;
rast_state.cullMode = state->rast_state->cull_mode;
- rast_state.frontFace = state->front_face;
+ rast_state.frontFace = state->dyn_state1.front_face;
rast_state.depthBiasEnable = VK_TRUE;
rast_state.depthBiasConstantFactor = 0.0;
VkPipelineDepthStencilStateCreateInfo depth_stencil_state = {0};
depth_stencil_state.sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO;
- depth_stencil_state.depthTestEnable = state->depth_stencil_alpha_state->depth_test;
- depth_stencil_state.depthCompareOp = state->depth_stencil_alpha_state->depth_compare_op;
- depth_stencil_state.depthBoundsTestEnable = state->depth_stencil_alpha_state->depth_bounds_test;
- depth_stencil_state.minDepthBounds = state->depth_stencil_alpha_state->min_depth_bounds;
- depth_stencil_state.maxDepthBounds = state->depth_stencil_alpha_state->max_depth_bounds;
- depth_stencil_state.stencilTestEnable = state->depth_stencil_alpha_state->stencil_test;
- depth_stencil_state.front = state->depth_stencil_alpha_state->stencil_front;
- depth_stencil_state.back = state->depth_stencil_alpha_state->stencil_back;
- depth_stencil_state.depthWriteEnable = state->depth_stencil_alpha_state->depth_write;
+ depth_stencil_state.depthTestEnable = state->dyn_state1.depth_stencil_alpha_state->depth_test;
+ depth_stencil_state.depthCompareOp = state->dyn_state1.depth_stencil_alpha_state->depth_compare_op;
+ depth_stencil_state.depthBoundsTestEnable = state->dyn_state1.depth_stencil_alpha_state->depth_bounds_test;
+ depth_stencil_state.minDepthBounds = state->dyn_state1.depth_stencil_alpha_state->min_depth_bounds;
+ depth_stencil_state.maxDepthBounds = state->dyn_state1.depth_stencil_alpha_state->max_depth_bounds;
+ depth_stencil_state.stencilTestEnable = state->dyn_state1.depth_stencil_alpha_state->stencil_test;
+ depth_stencil_state.front = state->dyn_state1.depth_stencil_alpha_state->stencil_front;
+ depth_stencil_state.back = state->dyn_state1.depth_stencil_alpha_state->stencil_back;
+ depth_stencil_state.depthWriteEnable = state->dyn_state1.depth_stencil_alpha_state->depth_write;
VkDynamicState dynamicStateEnables[30] = {
VK_DYNAMIC_STATE_LINE_WIDTH,
uint32_t hash;
bool dirty;
- struct zink_depth_stencil_alpha_hw_state *depth_stencil_alpha_state; //non-dynamic state
- VkFrontFace front_face;
-
+ struct {
+ struct zink_depth_stencil_alpha_hw_state *depth_stencil_alpha_state; //non-dynamic state
+ VkFrontFace front_face;
+ } dyn_state1;
+
bool primitive_restart; //dynamic state2
VkShaderModule modules[PIPE_SHADER_TYPES - 1];
hash = XXH32(&state->primitive_restart, 1, hash);
if (state->have_EXT_extended_dynamic_state)
return hash;
- return XXH32(&state->depth_stencil_alpha_state, sizeof(void*), hash);
+ return XXH32(&state->dyn_state1, sizeof(state->dyn_state1), hash);
}
static bool
if (sa->vertex_strides[idx_a] != sb->vertex_strides[idx_b])
return false;
}
- if (sa->front_face != sb->front_face)
+ if (sa->dyn_state1.front_face != sb->dyn_state1.front_face)
return false;
- if (!!sa->depth_stencil_alpha_state != !!sb->depth_stencil_alpha_state ||
- memcmp(sa->depth_stencil_alpha_state, sb->depth_stencil_alpha_state, sizeof(struct zink_depth_stencil_alpha_hw_state)))
+ if (!!sa->dyn_state1.depth_stencil_alpha_state != !!sb->dyn_state1.depth_stencil_alpha_state ||
+ memcmp(sa->dyn_state1.depth_stencil_alpha_state, sb->dyn_state1.depth_stencil_alpha_state, sizeof(struct zink_depth_stencil_alpha_hw_state)))
return false;
}
if (!sa->have_EXT_extended_dynamic_state2) {
if (cso) {
struct zink_gfx_pipeline_state *state = &ctx->gfx_pipeline_state;
- if (state->depth_stencil_alpha_state != &ctx->dsa_state->hw_state) {
- state->depth_stencil_alpha_state = &ctx->dsa_state->hw_state;
+ if (state->dyn_state1.depth_stencil_alpha_state != &ctx->dsa_state->hw_state) {
+ state->dyn_state1.depth_stencil_alpha_state = &ctx->dsa_state->hw_state;
state->dirty |= !zink_screen(pctx->screen)->info.have_EXT_extended_dynamic_state;
ctx->dsa_state_changed = true;
}
ctx->vp_state_changed = true;
}
- if (ctx->gfx_pipeline_state.front_face != ctx->rast_state->front_face) {
- ctx->gfx_pipeline_state.front_face = ctx->rast_state->front_face;
+ if (ctx->gfx_pipeline_state.dyn_state1.front_face != ctx->rast_state->front_face) {
+ ctx->gfx_pipeline_state.dyn_state1.front_face = ctx->rast_state->front_face;
ctx->gfx_pipeline_state.dirty |= !zink_screen(pctx->screen)->info.have_EXT_extended_dynamic_state;
}
if (ctx->rast_state->base.point_quad_rasterization != point_quad_rasterization)