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arm64: tegra: Add MISC registers on Tegra186
author
Thierry Reding
<treding@nvidia.com>
Mon, 26 Jun 2017 15:37:09 +0000
(17:37 +0200)
committer
Thierry Reding
<treding@nvidia.com>
Wed, 13 Dec 2017 12:15:42 +0000
(13:15 +0100)
The MISC register block found on Tegra186 SoCs contains registers that
can be used to identify a given chip and various strapping options.
Signed-off-by: Thierry Reding <treding@nvidia.com>
arch/arm64/boot/dts/nvidia/tegra186.dtsi
patch
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diff --git
a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index
46d1f28
..
11795db
100644
(file)
--- a/
arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/
arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@
-13,6
+13,12
@@
#address-cells = <2>;
#size-cells = <2>;
+ misc@100000 {
+ compatible = "nvidia,tegra186-misc";
+ reg = <0x0 0x00100000 0x0 0xf000>,
+ <0x0 0x0010f000 0x0 0x1000>;
+ };
+
gpio: gpio@2200000 {
compatible = "nvidia,tegra186-gpio";
reg-names = "security", "gpio";