#include "exec-memory.h"
+#define TYPE_TYPHOON_PCI_HOST_BRIDGE "typhoon-pcihost"
+
typedef struct TyphoonCchip {
MemoryRegion region;
uint64_t misc;
TyphoonWindow win[4];
} TyphoonPchip;
+#define TYPHOON_PCI_HOST_BRIDGE(obj) \
+ OBJECT_CHECK(TyphoonState, (obj), TYPE_TYPHOON_PCI_HOST_BRIDGE)
+
typedef struct TyphoonState {
PCIHostState host;
+
TyphoonCchip cchip;
TyphoonPchip pchip;
MemoryRegion dchip_region;
MemoryRegion *addr_space = get_system_memory();
MemoryRegion *addr_space_io = get_system_io();
DeviceState *dev;
- PCIHostState *p;
TyphoonState *s;
+ PCIHostState *phb;
PCIBus *b;
int i;
- dev = qdev_create(NULL, "typhoon-pcihost");
+ dev = qdev_create(NULL, TYPE_TYPHOON_PCI_HOST_BRIDGE);
qdev_init_nofail(dev);
- p = FROM_SYSBUS(PCIHostState, sysbus_from_qdev(dev));
- s = container_of(p, TyphoonState, host);
+ s = TYPHOON_PCI_HOST_BRIDGE(dev);
+ phb = FROM_SYSBUS(PCIHostState, SYS_BUS_DEVICE(dev));
/* Remember the CPUs so that we can deliver interrupts to them. */
for (i = 0; i < 4; i++) {
memory_region_add_subregion(addr_space, 0x801fc000000ULL,
&s->pchip.reg_io);
- b = pci_register_bus(&s->host.busdev.qdev, "pci",
+ b = pci_register_bus(dev, "pci",
typhoon_set_irq, sys_map_irq, s,
&s->pchip.reg_mem, addr_space_io, 0, 64);
- s->host.bus = b;
+ phb->bus = b;
/* Pchip0 PCI special/interrupt acknowledge, 0x801.F800.0000, 64MB. */
memory_region_init_io(&s->pchip.reg_iack, &alpha_pci_iack_ops, b,
}
static const TypeInfo typhoon_pcihost_info = {
- .name = "typhoon-pcihost",
+ .name = TYPE_TYPHOON_PCI_HOST_BRIDGE,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(TyphoonState),
.class_init = typhoon_pcihost_class_init,