The "Interrupt Enable" registers are sequential in the enum ni_gpct_register.
Replace this inline CamelCase function with a simple define.
Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com>
Reviewed-by: Ian Abbott <abbotti@mev.co.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
NITIO_DMA_CFG_REG(counter->counter_index), ~0,
0x0);
ni_tio_set_bits(counter,
- NITIO_Gi_Interrupt_Enable_Reg(counter->counter_index),
+ NITIO_INT_ENA_REG(counter->counter_index),
~0, 0x0);
}
EXPORT_SYMBOL_GPL(ni_tio_init_counter);
#define NITIO_ABZ_REG(x) (NITIO_G0_ABZ + (x))
#define NITIO_INT_ACK_REG(x) (NITIO_G0_INT_ACK + (x))
#define NITIO_STATUS_REG(x) (NITIO_G0_STATUS + (x))
-
-static inline enum ni_gpct_register NITIO_Gi_Interrupt_Enable_Reg(unsigned idx)
-{
- switch (idx) {
- case 0:
- return NITIO_G0_INT_ENA;
- case 1:
- return NITIO_G1_INT_ENA;
- case 2:
- return NITIO_G2_INT_ENA;
- case 3:
- return NITIO_G3_INT_ENA;
- }
- return 0;
-}
+#define NITIO_INT_ENA_REG(x) (NITIO_G0_INT_ENA + (x))
enum Gi_Auto_Increment_Reg_Bits {
Gi_Auto_Increment_Mask = 0xff
retval = ni_tio_set_gate_src(counter, 0, gate_source);
if (cmd->flags & TRIG_WAKE_EOS) {
ni_tio_set_bits(counter,
- NITIO_Gi_Interrupt_Enable_Reg(counter->
+ NITIO_INT_ENA_REG(counter->
counter_index),
Gi_Gate_Interrupt_Enable_Bit(counter->
counter_index),
ni_tio_configure_dma(counter, 0, 0);
ni_tio_set_bits(counter,
- NITIO_Gi_Interrupt_Enable_Reg(counter->counter_index),
+ NITIO_INT_ENA_REG(counter->counter_index),
Gi_Gate_Interrupt_Enable_Bit(counter->counter_index),
0x0);
return 0;