drm/exynos: ipp: Adapt IPPv2 code to older exynos & DRM frameworks

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Change-Id: I9547d3fcd2659a112f00cee51a9c3fc9d0abac8d

diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.c b/drivers/gpu/drm/exynos/exynos_drm_drv.c
index 9046b0d..df44d18 100644 (file)
--- a/drivers/gpu/drm/exynos/exynos_drm_drv.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_drv.c
@@ -28,10 +28,10 @@
 #include "exynos_drm_fb.h"
 #include "exynos_drm_gem.h"
 #include "exynos_drm_plane.h"
+#include "exynos_drm_ipp.h"
 #include "exynos_drm_vidi.h"
 #include "exynos_drm_dmabuf.h"
 #include "exynos_drm_g2d.h"
-#include "exynos_drm_ipp.h"
 #include "exynos_drm_iommu.h"
 #include "exynos_drm_debugfs.h"
 
@@ -265,13 +265,15 @@ static const struct drm_ioctl_desc exynos_ioctls[] = {
                        DRM_UNLOCKED | DRM_AUTH | DRM_RENDER_ALLOW),
        DRM_IOCTL_DEF_DRV(EXYNOS_G2D_EXEC, exynos_g2d_exec_ioctl,
                        DRM_UNLOCKED | DRM_AUTH | DRM_RENDER_ALLOW),
-       DRM_IOCTL_DEF_DRV(EXYNOS_IPP_GET_PROPERTY, exynos_drm_ipp_get_property,
+       DRM_IOCTL_DEF_DRV(EXYNOS_IPP_GET_RESOURCES,
+                       exynos_drm_ipp_get_res_ioctl,
                        DRM_UNLOCKED | DRM_AUTH | DRM_RENDER_ALLOW),
-       DRM_IOCTL_DEF_DRV(EXYNOS_IPP_SET_PROPERTY, exynos_drm_ipp_set_property,
+       DRM_IOCTL_DEF_DRV(EXYNOS_IPP_GET_CAPS, exynos_drm_ipp_get_caps_ioctl,
                        DRM_UNLOCKED | DRM_AUTH | DRM_RENDER_ALLOW),
-       DRM_IOCTL_DEF_DRV(EXYNOS_IPP_QUEUE_BUF, exynos_drm_ipp_queue_buf,
+       DRM_IOCTL_DEF_DRV(EXYNOS_IPP_GET_LIMITS,
+                       exynos_drm_ipp_get_limits_ioctl,
                        DRM_UNLOCKED | DRM_AUTH | DRM_RENDER_ALLOW),
-       DRM_IOCTL_DEF_DRV(EXYNOS_IPP_CMD_CTRL, exynos_drm_ipp_cmd_ctrl,
+       DRM_IOCTL_DEF_DRV(EXYNOS_IPP_COMMIT, exynos_drm_ipp_commit_ioctl,
                        DRM_UNLOCKED | DRM_AUTH | DRM_RENDER_ALLOW),
 };
 
@@ -387,12 +389,6 @@ static struct platform_driver *const exynos_drm_kms_drivers[] = {
 #ifdef CONFIG_DRM_EXYNOS_VIDI
        &vidi_driver,
 #endif
-};
-
-static struct platform_driver *const exynos_drm_non_kms_drivers[] = {
-#ifdef CONFIG_DRM_EXYNOS_G2D
-       &g2d_driver,
-#endif
 #ifdef CONFIG_DRM_EXYNOS_FIMC
        &fimc_driver,
 #endif
@@ -402,8 +398,14 @@ static struct platform_driver *const exynos_drm_non_kms_drivers[] = {
 #ifdef CONFIG_DRM_EXYNOS_GSC
        &gsc_driver,
 #endif
-#ifdef CONFIG_DRM_EXYNOS_IPP
-       &ipp_driver,
+#ifdef CONFIG_DRM_EXYNOS_SCALER
+       &scaler_driver,
+#endif
+};
+
+static struct platform_driver *const exynos_drm_non_kms_drivers[] = {
+#ifdef CONFIG_DRM_EXYNOS_G2D
+       &g2d_driver,
 #endif
        &exynos_drm_platform_driver,
 };
@@ -412,9 +414,6 @@ static struct platform_driver *const exynos_drm_drv_with_simple_dev[] = {
 #ifdef CONFIG_DRM_EXYNOS_VIDI
        &vidi_driver,
 #endif
-#ifdef CONFIG_DRM_EXYNOS_IPP
-       &ipp_driver,
-#endif
        &exynos_drm_platform_driver,
 };
 #define PDEV_COUNT ARRAY_SIZE(exynos_drm_drv_with_simple_dev)
@@ -436,7 +435,11 @@ static struct component_match *exynos_drm_match_add(struct device *dev)
                while ((d = bus_find_device(&platform_bus_type, p, drv,
                                            (void *)platform_bus_type.match))) {
                        put_device(p);
-                       component_match_add(dev, &match, compare_dev, d);
+
+                       if (!strstr(dev_name(d), "fimc") ||
+                           exynos_drm_check_fimc_device(d) == 0)
+                               component_match_add(dev, &match,
+                                                   compare_dev, d);
                        p = d;
                }
                put_device(p);

diff --git a/drivers/gpu/drm/exynos/exynos_drm_ipp.c b/drivers/gpu/drm/exynos/exynos_drm_ipp.c
index 9b4ffec..e5815a8 100644 (file)
--- a/drivers/gpu/drm/exynos/exynos_drm_ipp.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_ipp.c
@@ -28,6 +28,105 @@
 static int num_ipp;
 static LIST_HEAD(ipp_list);
 
+/*
+ * Internal function to query information for a given format. See
+ * drm_format_info() for the public API.
+ */
+const struct drm_format_info *__drm_format_info(u32 format)
+{
+       static const struct drm_format_info formats[] = {
+               { .format = DRM_FORMAT_C8,              .depth = 8,  .num_planes = 1, .cpp = { 1, 0, 0 }, .hsub = 1, .vsub = 1 },
+               { .format = DRM_FORMAT_RGB332,          .depth = 8,  .num_planes = 1, .cpp = { 1, 0, 0 }, .hsub = 1, .vsub = 1 },
+               { .format = DRM_FORMAT_BGR233,          .depth = 8,  .num_planes = 1, .cpp = { 1, 0, 0 }, .hsub = 1, .vsub = 1 },
+               { .format = DRM_FORMAT_XRGB4444,        .depth = 0,  .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 1, .vsub = 1 },
+               { .format = DRM_FORMAT_XBGR4444,        .depth = 0,  .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 1, .vsub = 1 },
+               { .format = DRM_FORMAT_RGBX4444,        .depth = 0,  .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 1, .vsub = 1 },
+               { .format = DRM_FORMAT_BGRX4444,        .depth = 0,  .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 1, .vsub = 1 },
+               { .format = DRM_FORMAT_ARGB4444,        .depth = 0,  .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 1, .vsub = 1 },
+               { .format = DRM_FORMAT_ABGR4444,        .depth = 0,  .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 1, .vsub = 1 },
+               { .format = DRM_FORMAT_RGBA4444,        .depth = 0,  .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 1, .vsub = 1 },
+               { .format = DRM_FORMAT_BGRA4444,        .depth = 0,  .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 1, .vsub = 1 },
+               { .format = DRM_FORMAT_XRGB1555,        .depth = 15, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 1, .vsub = 1 },
+               { .format = DRM_FORMAT_XBGR1555,        .depth = 15, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 1, .vsub = 1 },
+               { .format = DRM_FORMAT_RGBX5551,        .depth = 15, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 1, .vsub = 1 },
+               { .format = DRM_FORMAT_BGRX5551,        .depth = 15, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 1, .vsub = 1 },
+               { .format = DRM_FORMAT_ARGB1555,        .depth = 15, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 1, .vsub = 1 },
+               { .format = DRM_FORMAT_ABGR1555,        .depth = 15, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 1, .vsub = 1 },
+               { .format = DRM_FORMAT_RGBA5551,        .depth = 15, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 1, .vsub = 1 },
+               { .format = DRM_FORMAT_BGRA5551,        .depth = 15, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 1, .vsub = 1 },
+               { .format = DRM_FORMAT_RGB565,          .depth = 16, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 1, .vsub = 1 },
+               { .format = DRM_FORMAT_BGR565,          .depth = 16, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 1, .vsub = 1 },
+               { .format = DRM_FORMAT_RGB888,          .depth = 24, .num_planes = 1, .cpp = { 3, 0, 0 }, .hsub = 1, .vsub = 1 },
+               { .format = DRM_FORMAT_BGR888,          .depth = 24, .num_planes = 1, .cpp = { 3, 0, 0 }, .hsub = 1, .vsub = 1 },
+               { .format = DRM_FORMAT_XRGB8888,        .depth = 24, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1 },
+               { .format = DRM_FORMAT_XBGR8888,        .depth = 24, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1 },
+               { .format = DRM_FORMAT_RGBX8888,        .depth = 24, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1 },
+               { .format = DRM_FORMAT_BGRX8888,        .depth = 24, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1 },
+               { .format = DRM_FORMAT_XRGB2101010,     .depth = 30, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1 },
+               { .format = DRM_FORMAT_XBGR2101010,     .depth = 30, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1 },
+               { .format = DRM_FORMAT_RGBX1010102,     .depth = 30, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1 },
+               { .format = DRM_FORMAT_BGRX1010102,     .depth = 30, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1 },
+               { .format = DRM_FORMAT_ARGB2101010,     .depth = 30, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1 },
+               { .format = DRM_FORMAT_ABGR2101010,     .depth = 30, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1 },
+               { .format = DRM_FORMAT_RGBA1010102,     .depth = 30, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1 },
+               { .format = DRM_FORMAT_BGRA1010102,     .depth = 30, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1 },
+               { .format = DRM_FORMAT_ARGB8888,        .depth = 32, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1 },
+               { .format = DRM_FORMAT_ABGR8888,        .depth = 32, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1 },
+               { .format = DRM_FORMAT_RGBA8888,        .depth = 32, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1 },
+               { .format = DRM_FORMAT_BGRA8888,        .depth = 32, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1 },
+               { .format = DRM_FORMAT_YUV410,          .depth = 0,  .num_planes = 3, .cpp = { 1, 1, 1 }, .hsub = 4, .vsub = 4 },
+               { .format = DRM_FORMAT_YVU410,          .depth = 0,  .num_planes = 3, .cpp = { 1, 1, 1 }, .hsub = 4, .vsub = 4 },
+               { .format = DRM_FORMAT_YUV411,          .depth = 0,  .num_planes = 3, .cpp = { 1, 1, 1 }, .hsub = 4, .vsub = 1 },
+               { .format = DRM_FORMAT_YVU411,          .depth = 0,  .num_planes = 3, .cpp = { 1, 1, 1 }, .hsub = 4, .vsub = 1 },
+               { .format = DRM_FORMAT_YUV420,          .depth = 0,  .num_planes = 3, .cpp = { 1, 1, 1 }, .hsub = 2, .vsub = 2 },
+               { .format = DRM_FORMAT_YVU420,          .depth = 0,  .num_planes = 3, .cpp = { 1, 1, 1 }, .hsub = 2, .vsub = 2 },
+               { .format = DRM_FORMAT_YUV422,          .depth = 0,  .num_planes = 3, .cpp = { 1, 1, 1 }, .hsub = 2, .vsub = 1 },
+               { .format = DRM_FORMAT_YVU422,          .depth = 0,  .num_planes = 3, .cpp = { 1, 1, 1 }, .hsub = 2, .vsub = 1 },
+               { .format = DRM_FORMAT_YUV444,          .depth = 0,  .num_planes = 3, .cpp = { 1, 1, 1 }, .hsub = 1, .vsub = 1 },
+               { .format = DRM_FORMAT_YVU444,          .depth = 0,  .num_planes = 3, .cpp = { 1, 1, 1 }, .hsub = 1, .vsub = 1 },
+               { .format = DRM_FORMAT_NV12,            .depth = 0,  .num_planes = 2, .cpp = { 1, 2, 0 }, .hsub = 2, .vsub = 2 },
+               { .format = DRM_FORMAT_NV21,            .depth = 0,  .num_planes = 2, .cpp = { 1, 2, 0 }, .hsub = 2, .vsub = 2 },
+               { .format = DRM_FORMAT_NV16,            .depth = 0,  .num_planes = 2, .cpp = { 1, 2, 0 }, .hsub = 2, .vsub = 1 },
+               { .format = DRM_FORMAT_NV61,            .depth = 0,  .num_planes = 2, .cpp = { 1, 2, 0 }, .hsub = 2, .vsub = 1 },
+               { .format = DRM_FORMAT_NV24,            .depth = 0,  .num_planes = 2, .cpp = { 1, 2, 0 }, .hsub = 1, .vsub = 1 },
+               { .format = DRM_FORMAT_NV42,            .depth = 0,  .num_planes = 2, .cpp = { 1, 2, 0 }, .hsub = 1, .vsub = 1 },
+               { .format = DRM_FORMAT_YUYV,            .depth = 0,  .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
+               { .format = DRM_FORMAT_YVYU,            .depth = 0,  .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
+               { .format = DRM_FORMAT_UYVY,            .depth = 0,  .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
+               { .format = DRM_FORMAT_VYUY,            .depth = 0,  .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
+               { .format = DRM_FORMAT_AYUV,            .depth = 0,  .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1 },
+       };
+
+       unsigned int i;
+
+       for (i = 0; i < ARRAY_SIZE(formats); ++i) {
+               if (formats[i].format == format)
+                       return &formats[i];
+       }
+
+       return NULL;
+}
+
+/**
+ * drm_format_info - query information for a given format
+ * @format: pixel format (DRM_FORMAT_*)
+ *
+ * The caller should only pass a supported pixel format to this function.
+ * Unsupported pixel formats will generate a warning in the kernel log.
+ *
+ * Returns:
+ * The instance of struct drm_format_info that describes the pixel format, or
+ * NULL if the format is unsupported.
+ */
+static const struct drm_format_info *drm_format_info(u32 format)
+{
+       const struct drm_format_info *info;
+
+       info = __drm_format_info(format);
+       WARN_ON(!info);
+       return info;
+}
+
 /**
  * exynos_drm_ipp_register - Register a new picture processor hardware module
  * @dev: DRM device
@@ -339,7 +438,8 @@ static int exynos_drm_ipp_task_set(struct exynos_drm_ipp_task *task,
        return 0;
 }
 
-static int exynos_drm_ipp_task_setup_buffer(struct exynos_drm_ipp_buffer *buf,
+static int exynos_drm_ipp_task_setup_buffer(struct drm_device *dev,
+                                           struct exynos_drm_ipp_buffer *buf,
                                            struct drm_file *filp)
 {
        int ret = 0;
@@ -372,27 +472,27 @@ static int exynos_drm_ipp_task_setup_buffer(struct exynos_drm_ipp_buffer *buf,
                             DIV_ROUND_UP(buf->buf.height, buf->format->vsub);
                unsigned long size = height * buf->buf.pitch[i] +
                                     buf->buf.offset[i];
-               struct drm_gem_object *obj = drm_gem_object_lookup(filp,
+               struct drm_gem_object *obj = drm_gem_object_lookup(dev, filp,
                                                            buf->buf.gem_id[i]);
                if (!obj) {
                        ret = -ENOENT;
                        goto gem_free;
                }
-               buf->exynos_gem[i] = to_exynos_gem(obj);
+               buf->exynos_gem[i] = to_exynos_gem_obj(obj);
 
                if (size > buf->exynos_gem[i]->size) {
                        i++;
                        ret = -EINVAL;
                        goto gem_free;
                }
-               buf->dma_addr[i] = buf->exynos_gem[i]->dma_addr +
+               buf->dma_addr[i] = buf->exynos_gem[i]->buffer->dma_addr +
                                   buf->buf.offset[i];
        }
 
        return 0;
 gem_free:
        while (i--) {
-               drm_gem_object_put_unlocked(&buf->exynos_gem[i]->base);
+               drm_gem_object_unreference_unlocked(&buf->exynos_gem[i]->base);
                buf->exynos_gem[i] = NULL;
        }
        return ret;
@@ -405,7 +505,7 @@ static void exynos_drm_ipp_task_release_buf(struct exynos_drm_ipp_buffer *buf)
        if (!buf->exynos_gem[0])
                return;
        for (i = 0; i < buf->format->num_planes; i++)
-               drm_gem_object_put_unlocked(&buf->exynos_gem[i]->base);
+               drm_gem_object_unreference_unlocked(&buf->exynos_gem[i]->base);
 }
 
 static void exynos_drm_ipp_task_free(struct exynos_drm_ipp *ipp,
@@ -415,8 +515,18 @@ static void exynos_drm_ipp_task_free(struct exynos_drm_ipp *ipp,
 
        exynos_drm_ipp_task_release_buf(&task->src);
        exynos_drm_ipp_task_release_buf(&task->dst);
-       if (task->event)
-               drm_event_cancel_free(ipp->dev, &task->event->base);
+       if (task->event) {
+               struct drm_pending_event *p = &task->event->base;
+               struct drm_device *dev = ipp->dev;
+               unsigned long flags;
+
+               spin_lock_irqsave(&dev->event_lock, flags);
+               if (p->file_priv)
+                       p->file_priv->event_space += p->event->length;
+               spin_unlock_irqrestore(&dev->event_lock, flags);
+
+               kfree(p);
+       }
        kfree(task);
 }
 
@@ -640,12 +750,12 @@ static int exynos_drm_ipp_task_check(struct exynos_drm_ipp_task *task,
        if (ret)
                return ret;
 
-       ret = exynos_drm_ipp_task_setup_buffer(src, filp);
+       ret = exynos_drm_ipp_task_setup_buffer(ipp->dev, src, filp);
        if (ret) {
                DRM_DEBUG_DRIVER("Task %pK: src buffer setup failed\n", task);
                return ret;
        }
-       ret = exynos_drm_ipp_task_setup_buffer(dst, filp);
+       ret = exynos_drm_ipp_task_setup_buffer(ipp->dev, dst, filp);
        if (ret) {
                DRM_DEBUG_DRIVER("Task %pK: dst buffer setup failed\n", task);
                return ret;
@@ -656,6 +766,27 @@ static int exynos_drm_ipp_task_check(struct exynos_drm_ipp_task *task,
        return ret;
 }
 
+static int drm_event_reserve_init(struct drm_device *drm_dev,
+                                 struct drm_file *file_priv,
+                                 struct drm_pending_event *p,
+                                 struct drm_event *e)
+{
+       unsigned long flags;
+
+       spin_lock_irqsave(&drm_dev->event_lock, flags);
+       if (file_priv->event_space < e->length) {
+               spin_unlock_irqrestore(&drm_dev->event_lock, flags);
+               return -ENOMEM;
+       }
+       file_priv->event_space -= e->length;
+       spin_unlock_irqrestore(&drm_dev->event_lock, flags);
+
+       p->event = e;
+       p->file_priv = file_priv;
+       p->destroy = (void (*) (struct drm_pending_event *)) kfree;
+
+       return 0;
+}
 
 static int exynos_drm_ipp_event_create(struct exynos_drm_ipp_task *task,
                                 struct drm_file *file_priv, uint64_t user_data)
@@ -685,14 +816,20 @@ free:
 
 static void exynos_drm_ipp_event_send(struct exynos_drm_ipp_task *task)
 {
+       struct drm_device *drm_dev = task->ipp->dev;
+       struct drm_pending_exynos_ipp_event *e = task->event;
        struct timespec64 now;
+       unsigned long flags;
 
        ktime_get_ts64(&now);
-       task->event->event.tv_sec = now.tv_sec;
-       task->event->event.tv_usec = now.tv_nsec / NSEC_PER_USEC;
-       task->event->event.sequence = atomic_inc_return(&task->ipp->sequence);
-
-       drm_send_event(task->dev, &task->event->base);
+       e->event.tv_sec = now.tv_sec;
+       e->event.tv_usec = now.tv_nsec / NSEC_PER_USEC;
+       e->event.sequence = atomic_inc_return(&task->ipp->sequence);
+
+       spin_lock_irqsave(&drm_dev->event_lock, flags);
+       list_add_tail(&e->base.link, &e->base.file_priv->event_list);
+       wake_up_interruptible(&e->base.file_priv->event_wait);
+       spin_unlock_irqrestore(&drm_dev->event_lock, flags);
 }
 
 static int exynos_drm_ipp_task_cleanup(struct exynos_drm_ipp_task *task)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_ipp.h b/drivers/gpu/drm/exynos/exynos_drm_ipp.h
index 0b27d4a..670ed0d 100644 (file)
--- a/drivers/gpu/drm/exynos/exynos_drm_ipp.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_ipp.h
@@ -15,6 +15,42 @@
 struct exynos_drm_ipp;
 struct exynos_drm_ipp_task;
 
+#define DRM_MODE_ROTATE_0       (1<<0)
+#define DRM_MODE_ROTATE_90      (1<<1)
+#define DRM_MODE_ROTATE_180     (1<<2)
+#define DRM_MODE_ROTATE_270     (1<<3)
+#define DRM_MODE_REFLECT_X     (1<<4)
+#define DRM_MODE_REFLECT_Y     (1<<5)
+
+#define DRM_MODE_ROTATE_MASK (\
+            DRM_MODE_ROTATE_0  | DRM_MODE_ROTATE_90  | \
+            DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270)
+
+static inline bool drm_rotation_90_or_270(unsigned int rotation)
+{
+       return rotation & (DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270);
+}
+
+/**
+ * struct drm_format_info - information about a DRM format
+ * @format: 4CC format identifier (DRM_FORMAT_*)
+ * @depth: Color depth (number of bits per pixel excluding padding bits),
+ *     valid for a subset of RGB formats only. This is a legacy field, do not
+ *     use in new code and set to 0 for new formats.
+ * @num_planes: Number of color planes (1 to 3)
+ * @cpp: Number of bytes per pixel (per plane)
+ * @hsub: Horizontal chroma subsampling factor
+ * @vsub: Vertical chroma subsampling factor
+ */
+struct drm_format_info {
+       u32 format;
+       u8 depth;
+       u8 num_planes;
+       u8 cpp[3];
+       u8 hsub;
+       u8 vsub;
+};
+
 /**
  * struct exynos_drm_ipp_funcs - exynos_drm_ipp control functions
  */
@@ -75,7 +111,7 @@ struct exynos_drm_ipp_buffer {
        struct drm_exynos_ipp_task_buffer buf;
        struct drm_exynos_ipp_task_rect rect;
 
-       struct exynos_drm_gem *exynos_gem[MAX_FB_BUFFER];
+       struct exynos_drm_gem_obj *exynos_gem[MAX_FB_BUFFER];
        const struct drm_format_info *format;
        dma_addr_t dma_addr[MAX_FB_BUFFER];
 };

diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 0773582..208c53d 100644 (file)
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -143,6 +143,7 @@
 
 /* Vendor Ids: */
 #define DRM_FORMAT_MOD_NONE           0
+#define DRM_FORMAT_MOD_VENDOR_NONE    0
 #define DRM_FORMAT_MOD_VENDOR_INTEL   0x01
 #define DRM_FORMAT_MOD_VENDOR_AMD     0x02
 #define DRM_FORMAT_MOD_VENDOR_NV      0x03
@@ -161,6 +162,25 @@
  * authoritative source for all of these.
  */
 
+/*
+ * Invalid Modifier
+ *
+ * This modifier can be used as a sentinel to terminate the format modifiers
+ * list, or to initialize a variable with an invalid modifier. It might also be
+ * used to report an error back to userspace for certain APIs.
+ */
+#define DRM_FORMAT_MOD_INVALID fourcc_mod_code(NONE, DRM_FORMAT_RESERVED)
+
+/*
+ * Linear Layout
+ *
+ * Just plain linear layout. Note that this is different from no specifying any
+ * modifier (e.g. not setting DRM_MODE_FB_MODIFIERS in the DRM_ADDFB2 ioctl),
+ * which tells the driver to also take driver-internal information into account
+ * and so might actually result in a tiled framebuffer.
+ */
+#define DRM_FORMAT_MOD_LINEAR  fourcc_mod_code(NONE, 0)
+
 /* Intel framebuffer modifiers */
 
 /*
@@ -207,4 +227,19 @@
  */
 #define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3)
 
+
+/*
+ * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
+ *
+ * Macroblocks are laid in a Z-shape, and each pixel data is following the
+ * standard NV12 style.
+ * As for NV12, an image is the result of two frame buffers: one for Y,
+ * one for the interleaved Cb/Cr components (1/2 the height of the Y buffer).
+ * Alignment requirements are (for each buffer):
+ * - multiple of 128 pixels for the width
+ * - multiple of  32 pixels for the height
+ *
+ * For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html
+ */
+#define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE      fourcc_mod_code(SAMSUNG, 1)
 #endif /* DRM_FOURCC_H */