#error: interrupts not implemented yet
#endif
+#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#define TIMER_FREQ_HZ 3250000
+#elif defined(CONFIG_PXA250)
+#define TIMER_FREQ_HZ 3686400
+#else
+#error "Timer frequency unknown - please config PXA CPU type"
+#endif
+
int interrupt_init (void)
{
/* nothing happens here - we don't setup any IRQs */
ulong get_timer_masked (void)
{
- return OSCR;
+ unsigned long long ticks = get_ticks();
+
+ return (((ticks / TIMER_FREQ_HZ) * 1000) +
+ ((ticks % TIMER_FREQ_HZ) * 1000) / TIMER_FREQ_HZ);
}
void udelay_masked (unsigned long usec)
if (usec >= 1000) {
tmo = usec / 1000;
- tmo *= CONFIG_SYS_HZ;
+ tmo *= TIMER_FREQ_HZ;
tmo /= 1000;
} else {
- tmo = usec * CONFIG_SYS_HZ;
+ tmo = usec * TIMER_FREQ_HZ;
tmo /= (1000*1000);
}
- endtime = get_timer_masked () + tmo;
+ endtime = get_ticks() + tmo;
do {
- ulong now = get_timer_masked ();
+ ulong now = get_ticks();
diff = endtime - now;
} while (diff >= 0);
}
*/
unsigned long long get_ticks(void)
{
- return get_timer(0);
+ return OSCR;
}
/*
ulong get_tbclk (void)
{
ulong tbclk;
- tbclk = CONFIG_SYS_HZ;
+ tbclk = TIMER_FREQ_HZ;
return tbclk;
}
#define CONFIG_SYS_LOAD_ADDR 0xa2000000 /* default load address */
-#define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */
+#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 400/200/100 MHz */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CONFIG_SYS_LOAD_ADDR 0xa2000000 /* default load address */
-#define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */
+#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */
/* valid baudrates */
/* RS: is this where U-Boot is */
/* RS: relocated to in RAM? */
-#define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */
+#define CONFIG_SYS_HZ 1000
/* RS: the oscillator is actually 3680130?? */
#define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */
/* 0101000001 */
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DRAM_BASE + 0x8000) /* default load address */
-#define CONFIG_SYS_HZ 3250000 /* incrementer freq: 3.25 MHz */
+#define CONFIG_SYS_HZ 1000
/* Monahans Core Frequency */
#define CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO 16 /* valid values: 8, 16, 24, 31 */
#define CONFIG_SYS_LOAD_ADDR 0xa3000000 /* load kernel to this address */
-#define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */
+#define CONFIG_SYS_HZ 1000
/* RS: the oscillator is actually 3680130?? */
#define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */
#define CONFIG_SYS_LOAD_ADDR 0x08000000 /* load kernel to this address */
-#define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */
+#define CONFIG_SYS_HZ 1000
/* RS: the oscillator is actually 3680130?? */
#define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DRAM_BASE + 0x8000) /* default load address */
-#define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */
+#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */
/* valid baudrates */
#define CONFIG_SYS_LOAD_ADDR 0xa2000000 /* default load address */
-#define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */
+#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */
/* valid baudrates */
#define CONFIG_SYS_LOAD_ADDR 0xa0800000 /* default load address */
-#define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */
+#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */
#define RTC 1 /* enable 32KHz osc */
#define CONFIG_SYS_LOAD_ADDR 0xa1000000 /* default load address */
-#define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */
+#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_CPUSPEED 0x207 /* need to look more closely, I think this is Turbo = 2x, L=91Mhz */
/* valid baudrates */
#undef CONFIG_SYS_CLKS_IN_HZ /* use HZ for freq. display */
-#define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */
+#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_CPUSPEED 0x141 /* core clock - register value */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CONFIG_SYS_LOAD_ADDR 0xa1000000 /* default load address */
-#define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */
+#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 400/200/100 MHz */
/*
#define CONFIG_SYS_LOAD_ADDR 0xa3000000 /* default load address */
-#define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */
+#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_CPUSPEED 0x161 /* set core clock to 400/400/100 MHz */
/* valid baudrates */
#define CONFIG_DOS_PARTITION 1
#define BOARD_LATE_INIT 1
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
-#define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */
-
-#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
-#define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */
+#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DRAM_BASE + 0x8000) /* default load address */
-#define CONFIG_SYS_HZ 3250000 /* incrementer freq: 3.25 MHz */
+#define CONFIG_SYS_HZ 1000
/* Monahans Core Frequency */
#define CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO 16 /* valid values: 8, 16, 24, 31 */
projects / kernel / u-boot.git / commitdiff