ARM: socfpga: vining_fpga: Rename VINING|FPGA
authorMarek Vasut <marex@denx.de>
Wed, 26 Jun 2019 22:19:31 +0000 (00:19 +0200)
committermarex <marex@chi.lan>
Wed, 9 Oct 2019 20:54:17 +0000 (22:54 +0200)
The company Samtec was merged into Softing, migrate the board over to
the new name and update copyright headers.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Silvio Fricke <silvio.fricke@softing.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
arch/arm/dts/socfpga_cyclone5_vining_fpga.dts
arch/arm/mach-socfpga/Kconfig
board/softing/vining_fpga/MAINTAINERS [moved from board/samtec/vining_fpga/MAINTAINERS with 100% similarity]
board/softing/vining_fpga/Makefile [moved from board/samtec/vining_fpga/Makefile with 100% similarity]
board/softing/vining_fpga/qts/iocsr_config.h [moved from board/samtec/vining_fpga/qts/iocsr_config.h with 100% similarity]
board/softing/vining_fpga/qts/pinmux_config.h [moved from board/samtec/vining_fpga/qts/pinmux_config.h with 100% similarity]
board/softing/vining_fpga/qts/pll_config.h [moved from board/samtec/vining_fpga/qts/pll_config.h with 100% similarity]
board/softing/vining_fpga/qts/sdram_config.h [moved from board/samtec/vining_fpga/qts/sdram_config.h with 100% similarity]
board/softing/vining_fpga/socfpga.c [moved from board/samtec/vining_fpga/socfpga.c with 100% similarity]
configs/socfpga_vining_fpga_defconfig
include/configs/socfpga_vining_fpga.h

index ac57f41..be52fbf 100644 (file)
@@ -8,7 +8,7 @@
 #include <dt-bindings/input/input.h>
 
 / {
-       model = "samtec VIN|ING FPGA";
+       model = "Softing VIN|ING FPGA";
        compatible = "samtec,vining", "altr,socfpga-cyclone5", "altr,socfpga";
 
        chosen {
index 45de153..fc0a542 100644 (file)
@@ -100,8 +100,8 @@ config TARGET_SOCFPGA_IS1
        bool "IS1 (Cyclone V)"
        select TARGET_SOCFPGA_CYCLONE5
 
-config TARGET_SOCFPGA_SAMTEC_VINING_FPGA
-       bool "samtec VIN|ING FPGA (Cyclone V)"
+config TARGET_SOCFPGA_SOFTING_VINING_FPGA
+       bool "Softing VIN|ING FPGA (Cyclone V)"
        select BOARD_LATE_INIT
        select TARGET_SOCFPGA_CYCLONE5
 
@@ -145,7 +145,7 @@ config SYS_BOARD
        default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
        default "sr1500" if TARGET_SOCFPGA_SR1500
        default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
-       default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
+       default "vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
 
 config SYS_VENDOR
        default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
@@ -155,7 +155,7 @@ config SYS_VENDOR
        default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
        default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
        default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
-       default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
+       default "softing" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
        default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
        default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC
        default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO
@@ -178,6 +178,6 @@ config SYS_CONFIG_NAME
        default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
        default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
        default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
-       default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
+       default "socfpga_vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
 
 endif
index c52afdd..faa4a17 100644 (file)
@@ -1,6 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SOCFPGA=y
-CONFIG_TARGET_SOCFPGA_SAMTEC_VINING_FPGA=y
+CONFIG_TARGET_SOCFPGA_SOFTING_VINING_FPGA=y
 CONFIG_SPL_TEXT_BASE=0xFFFF0000
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
@@ -35,7 +35,7 @@ CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),64k(env1),64k(env2),256k(samtec1),256k(samtec2),-(rcvrfs);"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),64k(env1),64k(env2),256k(softing1),256k(softing2),-(rcvrfs);"
 CONFIG_CMD_UBI=y
 # CONFIG_ISO_PARTITION is not set
 # CONFIG_EFI_PARTITION is not set
@@ -86,7 +86,7 @@ CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_DWC2=y
 CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="samtec"
+CONFIG_USB_GADGET_MANUFACTURER="softing"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
 CONFIG_USB_GADGET_DWC2_OTG=y
index 232536a..ef3221e 100644 (file)
@@ -1,9 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Copyright (C) 2015 Marek Vasut <marex@denx.de>
+ * Copyright (C) 2015-2019 Marek Vasut <marex@denx.de>
  */
-#ifndef __CONFIG_SAMTEC_VINING_FPGA_H__
-#define __CONFIG_SAMTEC_VINING_FPGA_H__
+#ifndef __CONFIG_SOFTING_VINING_FPGA_H__
+#define __CONFIG_SOFTING_VINING_FPGA_H__
 
 #include <asm/arch/base_addr_ac5.h>
 
@@ -50,8 +50,8 @@
                "1m(u-boot),"                                           \
                "64k(env1),"                                            \
                "64k(env2),"                                            \
-               "256k(samtec1),"                                        \
-               "256k(samtec2),"                                        \
+               "256k(softing1),"                                       \
+               "256k(softing2),"                                       \
                "-(rcvrfs)\0"   /* Recovery */                          \
        "mtdparts_1=ff705000.spi.1:"                                    \
                "32m(rootfs),"                                          \
 /* The rest of the configuration is shared */
 #include <configs/socfpga_common.h>
 
-#endif /* __CONFIG_SAMTEC_VINING_FPGA_H__ */
+#endif /* __CONFIG_SOFTING_VINING_FPGA_H__ */