arm64: dts: qcom: sc7280: Add lpasscore & lpassaudio clock controllers

Add the low pass audio clock controller device nodes.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220202053207.14256-1-tdas@codeaurora.org

diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index ce766a8..e6571de 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -8,6 +8,8 @@
 #include <dt-bindings/clock/qcom,dispcc-sc7280.h>
 #include <dt-bindings/clock/qcom,gcc-sc7280.h>
 #include <dt-bindings/clock/qcom,gpucc-sc7280.h>
+#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
+#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
 #include <dt-bindings/clock/qcom,rpmh.h>
 #include <dt-bindings/clock/qcom,videocc-sc7280.h>
 #include <dt-bindings/gpio/gpio.h>
@@ -2028,6 +2030,47 @@
                        #clock-cells = <1>;
                };
 
+               lpass_audiocc: clock-controller@3300000 {
+                       compatible = "qcom,sc7280-lpassaudiocc";
+                       reg = <0 0x03300000 0 0x30000>;
+                       clocks = <&rpmhcc RPMH_CXO_CLK>,
+                              <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>;
+                       clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src";
+                       power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
+                       #clock-cells = <1>;
+                       #power-domain-cells = <1>;
+               };
+
+               lpass_aon: clock-controller@3380000 {
+                       compatible = "qcom,sc7280-lpassaoncc";
+                       reg = <0 0x03380000 0 0x30000>;
+                       clocks = <&rpmhcc RPMH_CXO_CLK>,
+                              <&rpmhcc RPMH_CXO_CLK_A>,
+                              <&lpasscore LPASS_CORE_CC_CORE_CLK>;
+                       clock-names = "bi_tcxo", "bi_tcxo_ao", "iface";
+                       #clock-cells = <1>;
+                       #power-domain-cells = <1>;
+               };
+
+               lpasscore: clock-controller@3900000 {
+                       compatible = "qcom,sc7280-lpasscorecc";
+                       reg = <0 0x03900000 0 0x50000>;
+                       clocks =  <&rpmhcc RPMH_CXO_CLK>;
+                       clock-names = "bi_tcxo";
+                       power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>;
+                       #clock-cells = <1>;
+                       #power-domain-cells = <1>;
+               };
+
+               lpass_hm: clock-controller@3c00000 {
+                       compatible = "qcom,sc7280-lpasshm";
+                       reg = <0 0x3c00000 0 0x28>;
+                       clocks = <&rpmhcc RPMH_CXO_CLK>;
+                       clock-names = "bi_tcxo";
+                       #clock-cells = <1>;
+                       #power-domain-cells = <1>;
+               };
+
                lpass_ag_noc: interconnect@3c40000 {
                        reg = <0 0x03c40000 0 0xf080>;
                        compatible = "qcom,sc7280-lpass-ag-noc";