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radv: Fix memory corruption loading RT pipeline cache entries.
author
Bas Nieuwenhuizen
<bas@basnieuwenhuizen.nl>
Sun, 14 Nov 2021 22:57:45 +0000
(23:57 +0100)
committer
Marge Bot
<emma+marge@anholt.net>
Tue, 16 Nov 2021 00:58:08 +0000
(
00:58
+0000)
Oops. Forgot to account for the size here.
Fixes:
ca2d96db51e
("radv: Add caching for RT pipelines.")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13789>
src/amd/vulkan/radv_pipeline_cache.c
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diff --git
a/src/amd/vulkan/radv_pipeline_cache.c
b/src/amd/vulkan/radv_pipeline_cache.c
index
3ea3693
..
0e8e515
100644
(file)
--- a/
src/amd/vulkan/radv_pipeline_cache.c
+++ b/
src/amd/vulkan/radv_pipeline_cache.c
@@
-109,6
+109,7
@@
entry_size(struct cache_entry *entry)
for (int i = 0; i < MESA_VULKAN_SHADER_STAGES; ++i)
if (entry->binary_sizes[i])
ret += entry->binary_sizes[i];
+ ret += sizeof(struct radv_pipeline_shader_stack_size) * entry->num_stack_sizes;
ret = align(ret, alignof(struct cache_entry));
return ret;
}