tu_cs_emit(cs, 0);
tu_cs_emit_regs(cs, A6XX_VFD_MULTIVIEW_CNTL());
- tu6_emit_vpc(cs, &vs, NULL, NULL, NULL, &fs, 0, false);
+ tu6_emit_vpc(cs, &vs, NULL, NULL, NULL, &fs, 0);
/* REPL_MODE for varying with RECTLIST (2 vertices only) */
tu_cs_emit_regs(cs, A6XX_VPC_VARYING_INTERP_MODE(0, 0));
const struct ir3_shader_variant *ds,
const struct ir3_shader_variant *gs,
const struct ir3_shader_variant *fs,
- uint32_t patch_control_points,
- bool vshs_workgroup)
+ uint32_t patch_control_points)
{
/* note: doesn't compile as static because of the array regs.. */
const struct reg_config {
tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_WAVE_INPUT_SIZE, 1);
tu_cs_emit(cs, 0);
- tu6_emit_vpc(cs, vs, hs, ds, gs, fs, cps_per_patch,
- builder->device->physical_device->gpu_id == 650);
+ tu6_emit_vpc(cs, vs, hs, ds, gs, fs, cps_per_patch);
tu6_emit_vpc_varying_modes(cs, fs);
bool no_earlyz = builder->depth_attachment_format == VK_FORMAT_S8_UINT;
const struct ir3_shader_variant *ds,
const struct ir3_shader_variant *gs,
const struct ir3_shader_variant *fs,
- uint32_t patch_control_points,
- bool vshs_workgroup);
+ uint32_t patch_control_points);
void
tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs);