risv:dts:starfive:Add timer clocktree

1.Modify the clock tree driver to make timer clock ignore disabled_unused.
2.Add different 'clock-frequency' node in fpga, evb and visionfive dts file.

Signed-off-by: xingyu.wu <xingyu.wu@starfivetech.com>

diff --git a/arch/riscv/boot/dts/starfive/jh7110-evb.dts b/arch/riscv/boot/dts/starfive/jh7110-evb.dts
index 4d0a08f..bce5855 100755 (executable)
--- a/arch/riscv/boot/dts/starfive/jh7110-evb.dts
+++ b/arch/riscv/boot/dts/starfive/jh7110-evb.dts
@@ -10,4 +10,8 @@
 / {
        model = "StarFive JH7110 EVB";
        compatible = "starfive,jh7110-evb", "starfive,jh7110";
+};
+
+&timer {
+       clock-frequency = <24000000>;
 };
\ No newline at end of file

diff --git a/arch/riscv/boot/dts/starfive/jh7110-fpga.dts b/arch/riscv/boot/dts/starfive/jh7110-fpga.dts
index 6a8dfd7..972f86f 100755 (executable)
--- a/arch/riscv/boot/dts/starfive/jh7110-fpga.dts
+++ b/arch/riscv/boot/dts/starfive/jh7110-fpga.dts
@@ -10,4 +10,12 @@
 / {
        model = "StarFive JH7110 FPGA";
        compatible = "starfive,jh7110-fpga", "starfive,jh7110";
+};
+
+&timer {
+       clock-frequency = <2000000>;
+};
+
+&wdog {
+       clock-frequency = <2000000>;
 };
\ No newline at end of file

diff --git a/arch/riscv/boot/dts/starfive/jh7110-visionfive-v2.dts b/arch/riscv/boot/dts/starfive/jh7110-visionfive-v2.dts
index 180113b..a311c85 100755 (executable)
--- a/arch/riscv/boot/dts/starfive/jh7110-visionfive-v2.dts
+++ b/arch/riscv/boot/dts/starfive/jh7110-visionfive-v2.dts
@@ -10,4 +10,8 @@
 / {
        model = "StarFive VisionFive V2";
        compatible = "starfive,visionfive-v2", "starfive,jh7110";
+};
+
+&timer {
+       clock-frequency = <24000000>;
 };
\ No newline at end of file

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index dcea9bd..aa986fa 100644 (file)
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -325,9 +325,17 @@
                        compatible = "starfive,si5-timers";
                        reg = <0x0 0x13050000 0x0 0x10000>;
                        interrupts = <69>, <70>, <71> ,<72>;
-                       interrupt-names = "timer0", "timer1", "timer2", "timer3";
+                       interrupt-names = "timer0", "timer1",
+                                         "timer2", "timer3";
+                       clocks = <&clkgen JH7110_TIMER_CLK_TIMER0>,
+                                <&clkgen JH7110_TIMER_CLK_TIMER1>,
+                                <&clkgen JH7110_TIMER_CLK_TIMER2>,
+                                <&clkgen JH7110_TIMER_CLK_TIMER3>,
+                                <&clkgen JH7110_TIMER_CLK_APB>;
+                       clock-names = "timer0", "timer1",
+                                     "timer2", "timer3", "apb_clk";
                        clock-frequency = <2000000>;
-                       status = "disabled";
+                       status = "okay";
                };
 
                wdog: wdog@13070000 {
@@ -337,10 +345,10 @@
                        interrupt-names = "wdog";
                        clock-frequency = <2000000>;
                        clocks = <&clkgen JH7110_DSKIT_WDT_CLK_WDT>,
-                               <&clkgen JH7110_DSKIT_WDT_CLK_APB>;
+                                <&clkgen JH7110_DSKIT_WDT_CLK_APB>;
                        clock-names = "core_clk", "apb_clk";
                        resets = <&rstgen RSTN_U0_DSKIT_WDT_APB>,
-                               <&rstgen RSTN_U0_DSKIT_WDT_CORE>;
+                                <&rstgen RSTN_U0_DSKIT_WDT_CORE>;
                        reset-names = "rst_apb", "rst_core";
                        timeout-sec = <15>;
                        status = "okay";

diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
index fb97283..c26d2ad 100755 (executable)
--- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c
+++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
@@ -285,15 +285,15 @@ static const struct jh7110_clk_data jh7110_clk_sys_data[] __initconst = {
                        0, JH7110_OSC),
        //TIMER
        JH7110_GATE(JH7110_TIMER_CLK_APB, "u0_si5_timer_clk_apb",
-                       0, JH7110_APB12),
+                       CLK_IGNORE_UNUSED, JH7110_APB12),
        JH7110_GATE(JH7110_TIMER_CLK_TIMER0, "u0_si5_timer_clk_timer0",
-                       0, JH7110_OSC),
+                       CLK_IGNORE_UNUSED, JH7110_OSC),
        JH7110_GATE(JH7110_TIMER_CLK_TIMER1, "u0_si5_timer_clk_timer1",
-                       0, JH7110_OSC),
+                       CLK_IGNORE_UNUSED, JH7110_OSC),
        JH7110_GATE(JH7110_TIMER_CLK_TIMER2, "u0_si5_timer_clk_timer2",
-                       0, JH7110_OSC),
+                       CLK_IGNORE_UNUSED, JH7110_OSC),
        JH7110_GATE(JH7110_TIMER_CLK_TIMER3, "u0_si5_timer_clk_timer3",
-                       0, JH7110_OSC),
+                       CLK_IGNORE_UNUSED, JH7110_OSC),
        //TEMP SENSOR
        JH7110_GATE(JH7110_TEMP_SENSOR_CLK_APB, "u0_temp_sensor_clk_apb",
                        0, JH7110_APB12),